54ACT16474 Datasheet | Texas Instruments

54ACT16474, 74ACT16474 18-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS238A - MAY 1992 - REVISED APRIL 1996 D Members of the Texas Instruments Widebus ™ Family D Inputs Are TTL-Voltage patible D 3-State Outputs Drive Bus Lines Directly D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configurations Minimize High-Speed Switching Noise D EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-m A Typical Latch-Up Immunity at 125°C D Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The ’ACT16474 are noninverting 18-bit registered bus transceivers posed of two 9-bit sections with separate control signals. For either 9-bit transceiver section, data flow in the A-to-B mode is controlled by output-enable (1OEAB or 2OEAB) and clock (1CLKAB or 2CLKAB) inputs. When 1OEAB or 2OEAB is low, the corresponding outputs are active (high or low) and take on either the current data on low-to-high transition of 1CLKAB or 2CLKAB or the previously stored data if 1CLKAB or 2CLKAB is low. 54ACT16474 . . . WD PACKAGE 74ACT16474 . . . DL PACKAGE (TOP VIEW) 1OEAB 1CLKAB 1A1 GND 1A2 1A3 VCC 1A4 1A5 1A6 GND 1A7 1A8 1A9 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2A9 2CLKAB 2OEAB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 1OEBA 55 1CLKBA 54 1B1 53 GND 52 1B2 51 1B3 50 VCC 49 1B4 48 1B5 47 1B6 46 GND 45 1B7 44 1B8 43 1B9 42 2B1 41 2B2 40 2B3 39 GND 38 2B4 37 2B5 36 2B6 35 VCC 34 2B7 33 2B8 32 GND 31 2B9 30 2CLKBA 29 2OEBA When 1OEAB or 2OEAB is high, the corresponding outputs are in the high-impedance state. 1OEAB or 2OEAB does not affect the operation on the internal registers. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. Data flow from B to A is similar,...