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66AK2E05, 66AK2E02
SPRS865D – NOVEMBER 2012 – REVISED MARCH 2015
66AK2E0x Multicore DSP+ARM KeyStone II System-on-Chip (SoC)
1 66AK2E0x Features and Description
1.1 Features
1
• ARM® Cortex®-A15 MPCore™ CorePac – Up to Four ARM Cortex-A15 Processor Cores at up to 1.4-GHz – 4MB L2 Cache Memory Shared by all CortexA15 Processor Cores – Full Implementation of ARMv7-A Architecture Instruction Set – 32KB L1 Instruction and Data Caches per Core – AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC (Multicore Shared Memory Controller) for Low Latency Access to SRAM and DDR3
• One TMS320C66x DSP Core Subsystem (C66x CorePacs), Each With – 1.4 GHz C66x Fixed/Floating-Point DSP Core • 38.
66AK2E02 Datasheet
