* AND-gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data. A low at either input inhibits entry of new data and resets the first flip-flop to the low level on the rising edge of the next clock pulse. A high-level input enables the
74AC11898 Datasheet (93.40 KB)
74AC11898
93.40 KB
10-bit parallel-out serial shift register.
ą 74AC11898 10ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą SCAS143 OCTOBER 1990 REVISED APRIL 1993 AND-Gated (Enable/Disab.
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