Datasheet4U Logo Datasheet4U.com

ADC12J4000 - 12-Bit A/D Converter

General Description

The ADC12J4000 device is a wideband sampling and digital tuning device.

Texas Instruments' giga-sample analog-to-digital converter (ADC) technology enables a large block of frequency spectrum to be sampled directly at RF.

Key Features

  • 1 Excellent Noise and Linearity up to and beyond FIN = 3 GHz.
  • Configurable DDC.
  • Decimation Factors from 4 to 32 (Complex Baseband Out).
  • Usable Output Bandwidth of 800 MHz at 4x Decimation and 4000 MSPS.
  • Usable Output Bandwidth of 100 MHz at 32x Decimation and 4000 MSPS.
  • Bypass Mode for Full Nyquist Output Bandwidth.
  • Low Pin-Count JESD204B Subclass 1 Interface.
  • Automatically Optimized Output Lane Count.
  • Embedded Low.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
ADC120 12-bit A/D converter STMicroelectronics
ADC12010 12-Bit/ 10 MSPS/ 160 mW A/D Converter National Semiconductor
ADC12020 12-Bit/ 20 MSPS/ 185 mW A/D Converter National Semiconductor
ADC12030 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters National Semiconductor
ADC12032 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
ADC12J1600 12-Bit A/D Converter
ADC12J2700 12-Bit A/D Converter
ADC12010 A/D Converter
ADC12020 A/D Converter
ADC12040 A/D Converter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Product Folder Order Now Technical Documents Tools & Software Support & Community ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 ADC12J4000 12-Bit, 4-GSPS ADC With Integrated DDC 1 Features •1 Excellent Noise and Linearity up to and beyond FIN = 3 GHz • Configurable DDC • Decimation Factors from 4 to 32 (Complex Baseband Out) • Usable Output Bandwidth of 800 MHz at 4x Decimation and 4000 MSPS • Usable Output Bandwidth of 100 MHz at 32x Decimation and 4000 MSPS • Bypass Mode for Full Nyquist Output Bandwidth • Low Pin-Count JESD204B Subclass 1 Interface • Automatically Optimized Output Lane Count • Embedded Low Latency Signal Range Indication • Low Power Consumption • Key Specifications: – Max Sampling Rate: 4000 MSPS – Min Sampling Rate: 1000 MSPS – DDC Output Word Size: 1