ADS5281 Datasheet | Texas Instruments

FEATURES - 234 Speed and Resolution Grades: - ADS5281: 12-bit, 50MSPS - ADS5282: 12-bit, 65MSPS - Power Dissipation: - 48m W/Channel at 30MSPS - 55m W/Channel at 40MSPS - 64m W/Channel at 50MSPS - 77m W/Channel at 65MSPS - 70d BFS SNR at 10MHz IF - Analog Input Full-Scale Range: 2VPP - Low-Frequency Noise Suppression Mode - 6d B Overload Recovery In One Clock - External and Internal (Trimmed) Reference - 3.3V Analog Supply, 1.8V Digital Supply - Single-Ended or Differential Clock: - Clock Duty Cycle Correction Circuit (DCC) - Programmable Digital Gain: 0d B to 12d B - Serialized DDR LVDS Output - Programmable LVDS Current Drive, Internal Termination - Test Patterns for Enabling Output Capture - Straight Offset Binary or Two's plement Output - Package Options: - 9mm × 9mm QFN-64 - HTQFP-80 Power PAD™ patible with ADS527x Family DESCRIPTION The ADS528x is a family of high-performance, lowpower, octal channel analog-to-digital converters (ADCs). Available in either a 9mm × 9mm QFN package or an HTQFP-80 package, with serialized low-voltage differential signaling (LVDS) outputs and a wide variety of programmable features , the ADS528x is highly customizable for a diversity of applications and offers an unprecedented level of system integration. An application note, XAPP774 (available at .xilinx.), describes how to interface the serial LVDS outputs of TI's ADCs to Xilinx® field-programmable gate arrays (FPGAs). The ADS528x family is specified over the industrial temperature range of - 40°C to +85°C. (ADCLK) CLKP (AVSS) CLKN AVDD (3.3V) LVDD (1.8V) ¼ ¼ ¼ ¼ ¼ ¼ Clock Buffer 6x ADCLK 12x ADCLK PLL 1x...