ADS58C48 Datasheet | Texas Instruments

FEATURES - Maximum Sample Rate: 200 MSPS - High Dynamic Performance - SFDR 82 d Bc at 140 MHz - 72.3 d BFS SNR in 60 MHz BW Using SNRBoost 3G technology - SNRBoost 3G Highlights - Supports Wide Bandwidth up to 60 MHz - Programmable Bandwidths - 60 MHz, 40 MHz, 30 MHz, 20 MHz - Flat Noise Floor within the Band - Independent SNRBoost 3G Coefficients for Every Channel - Output Interface - Double Data Rate (DDR) LVDS with Programmable Swing and Strength - Standard Swing: 350 m V - Low Swing: 200 m V - Default Strength: 100-Ω Termination - 2x Strength: 50-Ω Termination - 1.8V Parallel CMOS Interface Also Supported - Ultra-Low Power with Single 1.8-V Supply - 0.9-W Total Power - 1.32-W Total Power (200 MSPS) with SNRBoost 3G on all 4 Channels - 1.12-W Total Power (200 MSPS) with SNRBoost 3G on 2 Channels - Programmable Gain up to 6d B for SNR/SFDR Trade-Off - DC Offset Correction - Supports Low Input Clock Amplitude - 80-TQFP Package DESCRIPTION The ADS58C48 is a quad channel 11-bit A/D converter with sampling rate up to 200 MSPS. It uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This makes it well-suited for multi-carrier, wide band-width munications applications. The ADS58C48 uses third-generation SNRBoost 3G technology to overe SNR limitation due to quantization noise (for bandwidths < Nyquist, Fs/2). Enhancements in the SNRBoost 3G technology allow support for SNR improvements over wide bandwidths (up to 60 MHz). In addition, separate SNRBoost 3G coefficients can be programmed for each channel. The device has digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as DDR LVDS (Double Data Rate) together with an LVDS clock output. The low data rate of this interface (400 Mbps at 200 MSPS sample rate) makes it possible to...