ADS58J89
Description
The ADS58J89 is a high-linearity, quad-channel, 14bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems.
Key Features
- 1 4-Ch, 14-Bit 500MSPS With Digital Signal Processing
- Power Amplifier Linearization (Feedback) Modes - 14-Bits Every Other Sample at 250MSPS - Programmable Resolution vs Duty Cycle - Duty Cycle 3:2 (60% 11-Bit, 40% 9-Bit) - Duty Cycle 2:3 (40% 12-Bit, 60% 9-Bit) - Duty Cycle 1:3 (25% 14-Bit, 75% 9-Bit)
- Traffic Receiver Modes - 14-Bit 250MSPS: Decimate by 2 Filter, High/Low Pass - 9-Bit SNR-Boost Filter (150-MHz Max Bandwidth) - 9-to-14-Bit TDD Burst (200-MHz Max Bandwidth)
- Flexible Input Clock Buffer With Divide by 1/2/4
- JESD204B Digital Interface up to 5.0Gbps - 1 or 2 Lanes per Channel, With Subclass 1
- 64-Pin VQFN Package (9 × 9 mm)
