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ADS6144 - Analog-to-Digital Converters

Download the ADS6144 datasheet PDF. This datasheet also covers the ADS6142 variant, as both devices belong to the same analog-to-digital converters family and are provided as variant models within a single manufacturer datasheet.

Description

ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X) are a family of 14-bit A/D converters with sampling frequencies up to 125 MSPS.

The high performance and low power consumption of the ADS614X are combined in a compact 32 QFN package.

Features

  • 1.
  • Maximum Sample Rate: 125 MSPS.
  • 14-Bit Resolution with No Missing Codes.
  • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off.
  • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options.
  • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mVPP.
  • Clock Duty Cycle Stabilizer.
  • Internal Reference with Support for External Reference.
  • No External Decoupling Required for R.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADS6142-etcTI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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ADS60C120L 3 Quadrants Triacs ADV
ADS60C120S 3 Quadrants Triacs ADV
ADS60C160L 3 Quadrants Triacs ADV

Other Datasheets by Texas Instruments

Part Number Description
ADS6142 Analog-to-Digital Converters
ADS6143 Analog-to-Digital Converters
ADS6145 Analog-to-Digital Converters
ADS6148 Analog-to-Digital Converters
ADS6149 Analog-to-Digital Converters

Full PDF Text Transcription

Click to expand full text
www.ti.com ADS6145, ADS6144 ADS6143, ADS6142 SLWS198B – JULY 2007 – REVISED MARCH 2008 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS FEATURES 1 • Maximum Sample Rate: 125 MSPS • 14-Bit Resolution with No Missing Codes • 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR/SFDR Trade-Off • Parallel CMOS and Double Data Rate (DDR) LVDS Output Options • Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400 mVPP • Clock Duty Cycle Stabilizer • Internal Reference with Support for External Reference • No External Decoupling Required for References • Programmable Output Clock Position and Drive Strength to Ease Data Capture • 3.3-V Analog and 1.8-V to 3.
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