ADS62P42 Datasheet | Texas Instruments

ADS62P45, ADS62P44 ADS62P43, ADS62P42 .ti. SLAS561C - JULY 2007 - REVISED FEBRUARY 2012 DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Check for Samples: ADS62P45, ADS62P44, ADS62P43, ADS62P42 Features - Maximum Sample Rate: 125 MSPS - 14-Bit Resolution with No Missing Codes - 95 d B Crosstalk - Parallel CMOS and DDR LVDS Output Options - 3.5 d B Coarse Gain and Programmable Fine Gain up to 6 d B for SNR/SFDR Trade-Off - Digital Processing Block with: - Offset Correction - Fine Gain Correction, in Steps of 0.05 d B - Decimation by 2/4/8 - Built-in and Custom Programmable 24-Tap Low-/High-/Band-Pass Filters - Supports Sine, LVPECL, LVDS and LVCMOS Clocks and Amplitude Down to 400 m VPP - Clock Duty Cycle Stabilizer - Internal Reference; Supports External Reference also - 64-QFN Package (9mm × 9mm) - Pin patible 12-Bit Family (ADS62P2X) APPLICATIONS - Wireless munications Infrastructure - Software Defined...