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AM6548 Datasheet

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AM6548, AM6528, AM6546
AM6526, AM6527
SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019
AM654x, AM652x Sitara™ Processors
Silicon Revision 1.0
1 Device Overview
1.1 Features
1Processor cores:
• Dual- or quad-core Arm® Cortex®-A53
microprocessor subsystem at up to 1.1 GHz
– Up to two dual-core or two single-core Arm®
Cortex®-A53 clusters with 512KB L2 cache
including SECDED
– Each A53 core has 32KB L1 ICache and 32K L1
DCache
• Dual-core Arm® Cortex®-R5F at up to 400 MHz
– Supports lockstep mode
– 16KB ICache, 16KB DCache, and 64KB RAM
per R5F core
Industrial subsystem:
• Three gigabit Industrial Communication
Subsystems (PRU_ICSSG)
– Up to two 10/100/1000 Ethernet ports per
PRU_ICSSG
– Supports two SGMII ports (2)
– Compatibility with 10/100Mb PRU-ICSS
– 24× PWMs per PRU_ICSSG
– Cycle-by-cycle control
– Enhanced trip control
– 18× Sigma-delta filters per PRU_ICSSG
– Short circuit logic
– Over-current logic
– 6× Multi-protocol position encoder interfaces per
PRU_ICSSG
Memory subsystem:
• Up to 2MB of on-chip L3 RAM with SECDED
• Multi-core Shared Memory Controller (MSMC)
– Up to 2MB (2 banks × 1MB) SRAM with
SECDED
– Shared coherent Level 2 or Level 3 memory-
mapped SRAM
– Shared coherent Level 3 Cache
– 256-bit processor port bus and 40-bit physical
address bus
– Coherent unified bi-directional interfaces to
connect to processors or device masters
– L2, L3 Cache pre-warming and post flushing
– Bandwidth management with starvation bound
– One infrastructure master interface
– Single external memory master interface
– Supports distributed virtual system
– Supports internal DMA engine – Data Routing
1
Unit (DRU)
– ECC error protection
• DDR Subsystem (DDRSS)
– Supports DDR3L/DDR4 memory types up to
DDR-1600
– Supports LPDDR4 memory type up to DDR-
1333
– 32-bit data bus and 7-bit SECDED bus
– 32GB of total addressable space
• General-Purpose Memory Controller (GPMC)
SafeTI™ semiconductor component:
• Designed for functional safety applications
• Developed according to the requirements of IEC
61508
• Achieves systematic integrity of SIL-3
• For the MCU safety island, sufficient diagnostics
are included to achieve random fault integrity
requirements of SIL-2
• For the rest of the SoC, sufficient diagnostics are
included to achieve random fault integrity
requirements of SIL-2
• In addition, sufficient architectural metrics are in
place to achieve execution of SIL-3 applications
given a proper safety concept (for example
reciprocal comparison by software)
• Functional safety manual available
• Safety-related certification
– Component level functional safety certification
by TÜV SÜD [certification in progress]
• Functional safety features:
– ECC or parity on calculation-critical memories
and internal bus interconnect
– Firewalls to help provide Freedom From
Interference (FFI)
– Built-In Self-Test (BIST) for CPU, high-end
timers, and on-chip RAM
– Hardware error injection support for test-for-
diagnostics
– Error Signaling Modules (ESM) for capture of
functional safety related errors
– Voltage, temperature, and clock monitoring
– Windowed and non-windowed watchdog timers
in multiple clock domains
• MCU island
– Isolation of the dual-core Arm® Cortex®-R5F
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.




etcTI

AM6548 Datasheet Preview

AM6548 Datasheet

Processors

No Preview Available !

AM6548, AM6528, AM6546
AM6526, AM6527
SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019
www.ti.com
microprocessor subsystem
– Separate voltage, clocks, resets, and dedicated
peripherals
– Internal MCSPI connection to the rest of SoC
Security:
• Secure boot supported
– Hardware-enforced root-of-trust
– Support to switch root-of-trust via backup key
– Support for takeover protection, IP protection,
and anti-roll back protection
• Cryptographic acceleration supported
– Session-aware cryptographic engine with ability
to auto-switch key-material based on incoming
data stream
– Supports cryptographic cores
– AES – 128/192/256 bits key sizes
– 3DES – 56/112/168 bits key sizes
– MD5, SHA1
– SHA2 – 224/256/384/512
– DRBG with true random number generator
– PKA (public key accelerator) to assist in
RSA/ECC processing
– DMA support
• Debugging security
– Secure software controlled debug access
– Security aware debugging
• Trusted Execution Environment (TEE) supported
– Arm® TrustZone® based TEE
– Extensive firewall support for isolation
– Secure DMA path and interconnect
– Secure watchdog/timer/IPC
• Secure storage support
• On-the-fly encryption and authentication support
for OSPI interface
• Networking security support for data (payload)
encryption/authentication via packet based
hardware cryptographic engine
• Security co-processor (DMSC) for key and security
management, with dedicated device level
interconnect for security
SoC services:
• Device Management Security Controller (DMSC)
– Centralized SoC system controller
– Manages system services including initial boot,
security, functional safety and clock/reset/power
management
– Power management controller for active and low
power modes
– Communication with various processing units
over message manager
– Simplified interface for optimizing unused
peripherals
– Tracing and debugging capability
• Sixteen 32-bit general-purpose timers
• Two data movement and control Navigator
Subsystems (NAVSS)
– Ring Accelerator (RA)
– Unified DMA (UDMA)
– Up to 2 Timer Managers (TM) (1024 timers
each)
Multimedia:
• Display subsystem
– Two fully input-mapped overlay managers
associated with two display outputs
– One port MIPI® DPI parallel interface
– One port OLDI
• PowerVR® SGX544-MP1 3D Graphics Processing
Unit (GPU)
• One Camera Serial Interface-2 (MIPI CSI-2)
• One port video capture: BT.656/1120 (no
embedded sync)
High-speed interfaces:
• One Gigabit Ethernet (CPSW) interface supporting
– RMII (10/100) or RGMII (10/100/1000)
– IEEE1588 (2008 Annex D, Annex E, Annex F)
with 802.1AS PTP
– Audio/video bridging (P802.1Qav/D6.0)
– Energy-efficient Ethernet (802.3az)
– Jumbo frames (2024 bytes)
– Clause 45 MDIO PHY management
• Two PCI-Express® ( PCIe®) revision 3.1
subsystems (2)
– Supports Gen3 (8.0GT/s) operation
– Two independent 1-lane, or a single 2-lane port
– Support for concurrent root-complex and/or end-
point operation
• USB 3.1 Dual-Role Device (DRD) subsystem (2)
– One enhanced SuperSpeed Gen1 port
– One USB 2.0 port
– Each port independently configurable as USB
host, USB peripheral, or USB DRD
General connectivity:
• 6× Inter-Integrated Circuit ( I2C™) ports
• 5× configurable UART/IrDA/CIR modules
• Two simultaneous flash interfaces configured as
– Two OSPI flash interfaces
– or HyperBus™ and OSPI1 flash interface
• 2× 12-bit Analog-to-Digital Converters (ADC)
– Up to 4 Msamples/s
– Eight multiplexed analog inputs
• 8× Multichannel Serial Peripheral Interfaces
(MCSPI) controllers
– Two with internal connections
– Six with external interfaces
• General-Purpose I/O (GPIO) pins
Control interfaces:
• 6× Enhanced High Resolution Pulse-Width
2 Device Overview
Copyright © 2017–2019, Texas Instruments Incorporated
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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527


Part Number AM6548
Description Processors
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