Datasheet Summary
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCHS325
- JANUARY 2003
D AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the
Supply Voltage
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays D ±24-mA Output Drive Current
- Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
CD54AC112 . . . F PACKAGE CD74AC112 . . . E OR M PACKAGE
(TOP VIEW)
1CLK 1 1K 2 1J 3
1PRE 4 1Q 5 1Q 6 2Q 7
GND 8
16 VCC 15 1CLR 14 2CLR 13 2CLK 12 2K 11 2J 10 2PRE 9 2Q description/ordering information
The...