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CD54HC4024 - 7-Stage Binary Ripple Counter

Description

Fully Static Operation Buffered Inputs Common Reset Negative Edge Clocking Fanout (Over Temperature Range) - Standard Outputs 10 LSTTL Loads - Bus Driver Outputs

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Wide Operat

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Data sheet acquired from Harris Semiconductor SCHS202C November 1997 - Revised October 2003 CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 High-Speed CMOS Logic 7-Stage Binary Ripple Counter [ /Title (CD74 HC402 4, CD74 HCT40 24) /Subject (High Speed CMOS Features Description • Fully Static Operation • Buffered Inputs • Common Reset • Negative Edge Clocking • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . .
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