Datasheet Summary
Data sheet acquired from Harris Semiconductor SCHS141H
March 1998
- Revised October 2003
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
[ /Title (CD74 HC112 , CD74 HCT11 2) /Subject (Dual J-K FlipFlop with Set and Reset Nega-
Features
Description
- Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
- Asynchronous Set and Reset
- plementary Outputs
- Buffered Inputs
- TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF,
- Fanout (Over Temperature Range)
- Standard Outputs
- -
- 10 LSTTL Loads
- Bus Driver Outputs
- - . . . 15 LSTTL Loads
- Wide...