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CD54HCT4024 Datasheet Preview

CD54HCT4024 Datasheet

7-Stage Binary Ripple Counter

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Data sheet acquired from Harris Semiconductor
SCHS202C
November 1997 - Revised October 2003
CD54HC4024, CD74HC4024,
CD54HCT4024, CD74HCT4024
High-Speed CMOS Logic
7-Stage Binary Ripple Counter
[ /Title
(CD74
HC402
4,
CD74
HCT40
24)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary
counters. All counter stages are master-slave flip-flops. The
state of the stage advances one count on the negative
transition of each input pulse; a high voltage level on the MR
line resets all counters to their zero state. All inputs and
outputs are buffered.
Ordering Information
PART NUMBER
CD54HC4024F3A
CD54HCT4024F3A
CD74HC4024E
CD74HC4024M
CD74HC4024MT
CD74HC4024M96
CD74HC4024PW
CD74HC4024PWR
CD74HC4024PWT
CD74HCT4024E
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld PDIP
CD74HCT4024M
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
Pinout
CD54HC4024, CD54HCT4024
(CERDIP)
CD74HC4024
(PDIP, SOIC, TSSOP)
CD74HCT4024
(PDIP, SOIC)
TOP VIEW
CP 1
MR 2
Q7 3
Q6 4
Q5 5
Q4 6
GND 7
14 VCC
13 NC
12 Q1
11 Q2
10 NC
9 Q3
8 NC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




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CD54HCT4024 Datasheet Preview

CD54HCT4024 Datasheet

7-Stage Binary Ripple Counter

No Preview Available !

CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024
Functional Diagram
1
CP
2
MR
12
Q1
11
Q2
9
Q3
6
Q4
5
Q5
4
Q6
3
Q7
TRUTH TABLE
CP COUNT
MR
OUTPUT STATE
L
No Change
L
Advance to Next State
XH
All Outputs Are Low
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
= Transition from Low to High Level, = Transition from High to Low.
Logic Diagram
1
CP
2
MR
7
GND
14
VCC
CP Q
1 Q1
CP Q
R
CP Q
2
CP Q
R
CP Q
3
CP Q
R
CP Q
4
CP Q
R
CP Q
5
CP Q
R
CP Q
6
CP Q
R
CP Q
7
CP Q
R
12
Q1
11
Q2
9
Q3
6
Q4
5
Q5
4
Q6
3
Q7
2


Part Number CD54HCT4024
Description 7-Stage Binary Ripple Counter
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CD54HCT4024 Datasheet PDF






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