Datasheet Details
| Part number | CD74ACT109 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 475.21 KB |
| Description | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Datasheet | CD74ACT109-etcTI.pdf |
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Overview: CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54ACT109 . . . F PACKAGE CD74ACT109 . . .
| Part number | CD74ACT109 |
|---|---|
| Manufacturer | Texas Instruments |
| File Size | 475.21 KB |
| Description | DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS |
| Datasheet | CD74ACT109-etcTI.pdf |
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|
/ordering information The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
| Part Number | Description |
|---|---|
| CD74ACT10 | TRIPLE 3-INPUT POSITIVE-NAND GATES |
| CD74ACT112 | DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS |
| CD74ACT138 | 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS |
| CD74ACT139 | DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS |
| CD74ACT14 | Hex Schmitt-Trigger Inverter |
| CD74ACT151 | 8-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS |
| CD74ACT153 | DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS |
| CD74ACT157 | QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER |
| CD74ACT158 | QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER |
| CD74ACT161 | 4-BIT SYNCHRONOUS BINARY COUNTERS |