Datasheet Summary
CD54ACT109, CD74ACT109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SCHS327
- JANUARY 2003
D Inputs Are TTL-Voltage patible D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays D ±24-mA Output Drive Current
- Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
CD54ACT109 . . . F PACKAGE CD74ACT109 . . . E OR M PACKAGE
(TOP VIEW)
1CLR 1 1J 2 1K 3
1CLK 4 1PRE 5
1Q 6 1Q 7 GND 8
16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q description/ordering information
The ’ACT109 devices contain two independent J-K positive-edge-tr...