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CD74HC273 Datasheet Preview

CD74HC273 Datasheet

Octal D-Type Flip-Flop

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Data sheet acquired from Harris Semiconductor
SCHS174B
February 1998 - Revised May 2003
CD54HC273, CD74HC273,
CD54HCT273, CD74HCT273
High-Speed CMOS Logic
Octal D-Type Flip-Flop with Reset
[ /Title
(CD74
HC273
,
CD74
HCT27
3)
/Sub-
ject
(High
Speed
CMOS
Logic
Octal
D-
Type
Flip-
Features
Description
• Common Clock and Asynchronous Master Reset
• Positive Edge Triggering
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC273 and ’HCT273 high speed octal D-Type flip-flops
with a direct clear input are manufactured with silicon-gate
CMOS technology. They possess the low power consumption
of standard CMOS integrated circuits.
Information at the D inputis transferred to the Q outputs on
the positive-going edge of the clock pulse. All eight flip-flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All eight Q outputs are reset to a
logic 0.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
CD54HC273F3A
-55 to 125
20 Ld CERDIP
CD74HC273E
-55 to 125
20 Ld PDIP
CD74HC273M
-55 to 125
20 Ld SOIC
CD74HC273M96
-55 to 125
20 Ld SOIC
CD54HCT273F3A
-55 to 125
20 Ld CERDIP
CD74HCT273E
-55 to 125
20 Ld PDIP
CD74HCT273M
-55 to 125
20 Ld SOIC
CD74HCT273M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
Pinout
CD54HC273, CD54HCT273
(CERDIP)
CD74HC273, CD74HCT273
(PDIP, SOIC)
TOP VIEW
MR 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




etcTI

CD74HC273 Datasheet Preview

CD74HC273 Datasheet

Octal D-Type Flip-Flop

No Preview Available !

Functional Diagram
CD54/74HC273, CD54/74HCT273
CLOCK
CP
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3 DATA
Q4 OUTPUTS
Q5
Q6
Q7
RESET MR
TRUTH TABLE
INPUTS
OUTPUT
RESET (MR)
L
CLOCK CP
X
DATA Dn
X
Q
L
H HH
H LL
H L X Q0
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, = Transition from Low to
High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established.
2


Part Number CD74HC273
Description Octal D-Type Flip-Flop
Maker etcTI
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CD74HC273 Datasheet PDF






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