CD74HC4024 Datasheet | Texas Instruments

Features Description - Fully Static Operation - Buffered Inputs - mon Reset - Negative Edge Clocking - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V - HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic patibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input patibility, Il ≤ 1µA at VOL, VOH The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered. Ordering Information PART NUMBER CD54HC4024F3A CD54HCT4024F3A CD74HC4024E CD74HC4024M CD74HC4024MT CD74HC4024M96 CD74HC4024PW CD74HC4024PWR CD74HC4024PWT CD74HCT4024E TEMP. RANGE (o C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 14 Ld CERDIP 14 Ld CERDIP 14 Ld PDIP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld PDIP CD74HCT4024M -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC4024, CD54HCT4024 (CERDIP) CD74HC4024 (PDIP, SOIC, TSSOP) CD74HCT4024 (PDIP, SOIC) TOP VIEW CP 1 MR 2 Q7 3 Q6 4 Q5 5 Q4 6 GND 7 14 VCC 13 NC 12 Q1’ 11 Q2 10 NC 9 Q3 8 NC CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling...