CD74HC4094E Datasheet | Texas Instruments

Features - Buffered inputs - Separate serial outputs synchronous to both positive and negative clock edges for cascading - Fanout (over temperature range) - Standard outputs: 10 LSTTL loads - Bus driver outputs: 15 LSTTL loads - Wide operating temp range: - 55°C to 125°C - Balanced propagation delay and transition times - Significant power reduction pared to LSTTL logic ICs - HC types - 2- to 6-V operation - High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V - HCT types - 4.5- to 5.5-V operation - Direct LSTTL input logic patibility, VIL= 0.8 V (Max), VIH = 2 V (Min) - CMOS input patibility, Il ≤ 1μA at VOL, VOH 2 Description The CDx4HC4094 and CD74HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input to parallel buffered tri-state outputs. The parallel outputs may be connected directly to mon bus lines. Data is shifted on positive clock transitions. The data in each shift register stage is transferred to the storage register when the Strobe input is high. Data in the storage register appears at the outputs whenever the Output-Enable signal is high. PART NUMBER Device Information PACKAGE(1) BODY SIZE (NOM) CD54HC4094F3A CDIP (16) 24.38 mm × 6.92 mm CD74HC4094M SOIC (16) 9.90 mm × 3.90 mm PDIP (16) 19.31 mm × 6.35 mm CD74HC4094NSR SO (16) 6.20 mm × 5.30 mm CD74HC4094PW TSSOP (16) 5.00 mm × 4.40 mm CD74HCT4094M SOIC (16) 9.90 mm × 3.90 mm CD74HCT4094E PDIP (16) 19.31 mm × 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. OE...