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CD74HC4514E Datasheet Preview

CD74HC4514E Datasheet

4-TO-16 LINE DECODER/DEMULTIPLEXER

No Preview Available !

Data sheet acquired from Harris Semiconductor
SCHS280C
November 1997 - Revised July 2003
CD54HC4514, CD74HC4514,
CD74HC4515
High-Speed CMOS Logic 4- to 16-Line
Decoder/Demultiplexer with Input Latches
[ /Title
(CD74
HC451
4,
CD74
HC451
5)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Multifunction Capability
- Binary to 1-of-16 Decoder
- 1-to-16 Line Demultiplexer
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
The CD54HC4514, CD74HC4514, and CD74HC4515 are
high-speed silicon gate devices consisting of a 4-bit strobed
latch and a 4- to 16-line decoder. The selected output is
enabled by a low on the enable input (E). A high on E inhibits
selection of any output. Demultiplexing is accomplished by
using the E input as the data input and the select inputs (A0-
A3) as addresses. This E input also serves as a chip select
when these devices are cascaded.
When Latch Enable (LE) is high the output follows changes
in the inputs (see truth table). When LE is low the output is
isolated from changes in the input and remains at the level
(high for the 4514, low for the 4515) it had before the latches
were enabled. These devices, enhanced versions of the
equivalent CMOS types, can drive 10 LSTTL loads.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
Pinout
CD54HC4514
(CERDIP)
CD74HC4514, CD74HC4515
(PDIP, SOIC)
TOP VIEW
CD54HC4514F3A
CD74HC4514E
CD74HC4514EN
CD74HC4514M
CD74HC4514M96
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
24 Ld CERDIP
24 Ld PDIP
24 Ld PDIP
24 Ld SOIC
24 Ld SOIC
LE 1
A0 2
A1 3
Y7 4
Y6 5
Y5 6
Y4 7
Y3 8
Y1 9
Y2 10
Y0 11
GND 12
24 VCC
23 E
22 A3
21 A2
20 Y10
19 Y11
18 Y8
17 Y9
16 Y14
15 Y15
14 Y12
13 Y13
CD74HC4515E
-55 to 125
24 Ld PDIP
CD74HC4515EN
-55 to 125
24 Ld PDIP
CD74HC4515M
-55 to 125
24 Ld SOIC
CD74HC4515M96
-55 to 125
24 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




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CD74HC4514E Datasheet Preview

CD74HC4514E Datasheet

4-TO-16 LINE DECODER/DEMULTIPLEXER

No Preview Available !

CD54HC4514, CD74HC4514, CD74HC4515
Functional Diagram
HC
HC
4514 4515
11 Y0 Y0
9 Y1 Y1
10 Y2 Y2
8 Y3 Y3
2
A0
7 Y4 Y4
6 Y5 Y5
A1
A2
A3
3
21 LATCH
22
4-TO-16
DECODER
5 Y6
4
18 Y7
17 Y8
20 Y9
Y6
Y7
Y8
Y9
1
LE
19 Y10 Y10
14 Y11 Y11
13 Y12 Y12
16 Y13 Y13
15 Y14 Y14
Y15 Y15
23
E
GND = 12
VCC = 24
ENABLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
DECODE TRUTH TABLE (LE = 1)
DECODER INPUTS
A3
A2
A1
A0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
X
X
X
X
X = Don’t Care; Logic 1 = High; Logic 0 = Low
ADDRESSED OUTPUT
4514 = LOGIC 1 (HIGH)
4515 = LOGIC 0 (HIGH)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
All Outputs = 0, 4514
All Outputs = 1, 4515
2


Part Number CD74HC4514E
Description 4-TO-16 LINE DECODER/DEMULTIPLEXER
Maker etcTI
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CD74HC4514E Datasheet PDF






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