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CD74HC563 Datasheet Preview

CD74HC563 Datasheet

Octal Inverting Transparent Latch

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Data sheet acquired from Harris Semiconductor
SCHS187C
January 1998 - Revised July 2003
CD54/74HC533, CD54/74HCT533,
CD54/74HC563, CD74HCT563
High-Speed CMOS Logic Octal Inverting
Transparent Latch, Three-State Outputs
[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
Speed
Features
Description
• Common Latch-Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• TCyLp=ic1a5l pPFr,oTpAag=a2ti5oonCD(eDlaatya=to13Onustpaut tV) CC = 5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC533, ’HCT533, ’HC563, and CD74HCT563 are
high-speed Octal Transparent Latches manufactured with
silicon gate CMOS technology. They possess the low power
consumption of standard CMOS integrated circuits, as well as
the ability to drive 15 LSTTL devices.
The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the
three-state outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
is independent of the state of the output enable.
The ’HC533 and ’HCT533 are identical in function to the
’HC563 and CD74HCT563 but have different pinouts. The
’HC533 and ’HCT533 are similar to the ’HC373 and ’HCT373;
the latter are non-inverting types.
Ordering Information
PART NUMBER
CD54HC533F3A
CD54HC563F3A
CD54HCT533F3A
CD74HC533E
CD74HC563E
CD74HC563M
CD74HCT533E
CD74HCT563E
CD74HCT563M
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




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CD74HC563 Datasheet Preview

CD74HC563 Datasheet

Octal Inverting Transparent Latch

No Preview Available !

CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
Pinouts
CD54HC533, CD54HCT533
(CERDIP)
CD74HC533, CD74HCT533
(PDIP)
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
CD54HC563
(CERDIP)
CD74HC563, CD74HCT563
(PDIP, SOIC)
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Functional Block Diagram
HC/HCT533
D0
D1
D2
D3
D4
D5
D6
D7
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
TRUTH TABLE
OUTPUT ENABLE
LATCH ENABLE
DATA
Q OUTPUT
L
H
H
L
L
H
L
H
L
L
l
H
L
L
h
L
H
X
X
Z
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to
the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
2


Part Number CD74HC563
Description Octal Inverting Transparent Latch
Maker etcTI
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CD74HC563 Datasheet PDF






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