CD74HC646 Datasheet | Texas Instruments

Features Description - Independent Registers for A and B Buses - Non-Inverting - Three-State Outputs - Drives 15 LSTTL Loads - Typical Propagation Delay = 12ns (A to B, B to A) at VCC = 5V, CL = 15p F, TA = 25o C - Fanout (Over Temperature Range) - Standard Outputs - - - 10 LSTTL Loads - Bus Driver Outputs - - . . . 15 LSTTL Loads - Wide Operating Temperature Range . . . -55o C to 125o C - Balanced Propagation Delay and Transition Times - Significant Power Reduction pared to LSTTL Logic ICs - HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V The CD74HC646 is an octal bus transceiver/register with three-state non-inverting outputs. This device is a bus transceiver with D-type flip-flops which act as internal storage registers. Data on the A bus or the B bus can be clocked into the registers on the Low-to-High transition of either CAB or CBA clock inputs. Outputs enable (OE) and direction (DIR) inputs control the transceiver functions. Data present at the high impedance output can be stored in either register or both but only one of the two buses can be enabled as outputs at any one time. The select controls (SAB and SBA) can multiplex stored and transparent (real time) data. The direction control determines which data bus will receive data when the output enable (OE) is Low. In the high impedance mode (output enable High), A data can be stored in one register and B data can be stored in the other register. The clocks are not gated with the direction (DIR) and output enable (OE) terminals; data at the A or B terminals can be clocked into the storage flip-flops at any time. Ordering Information PART NUMBER TEMP. RANGE (o C) PACKAGE Pinout CD74HC646 (SOIC) TOP VIEW CD74HC646M -55 to 125 24 Ld SOIC CD74HC646M96 -55 to 125 24 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. CAB 1 SAB 2 DIR 3 A0 4 A1 5 A2 6 A3 7 A4 8 A5 9 A6 10 A7 11...