* LSTTL input logic compatible
  – VIL(max) = 0.8 V, VIH(min) = 2 V
* CMOS input logic compatible
  – II ≤ 1 µA at VOL, VOH
* Buff.

* User fewer inputs to monitor error signals
* Combine active-low enable signals 3 Description This device con.

This device contains three independent 3-input OR gates. Each gate performs the Boolean function Y = A + B + C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT4075E PDIP (14) 19.30 mm × 6.40 mm CD54HCT4075.

CD74HCT4075E

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