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CD74HCT4075 - Triple 3-Input OR Gate

Download the CD74HCT4075 datasheet PDF. This datasheet also covers the CD74HC4075 variant, as both devices belong to the same triple 3-input or gate family and are provided as variant models within a single manufacturer datasheet.

Description

This device contains three independent 3-input OR gates.

Each gate performs the Boolean function Y = A + B + C in positive logic.

Features

  • LSTTL input logic compatible.
  • VIL(max) = 0.8 V, VIH(min) = 2 V.
  • CMOS input logic compatible.
  • II ≤ 1 µA at VOL, VOH.
  • Buffered inputs.
  • 4.5 V to 5.5 V operation.
  • Wide operating temperature range: -55°C to +125°C.
  • Supports fanout up to 10 LSTTL loads.
  • Significant power reduction compared to LSTTL logic ICs 2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD74HC4075-etcTI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD74HCT4075, CD54HCT4075 SCHS408 – JUNE 2020 CDx4HCT4075 Triple 3-Input OR Gates 1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 µA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • User fewer inputs to monitor error signals • Combine active-low enable signals 3 Description This device contains three independent 3-input OR gates. Each gate performs the Boolean function Y = A + B + C in positive logic. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CD74HCT4075E PDIP (14) 19.30 mm × 6.40 mm CD54HCT4075F CDIP (14) 21.30 mm × 7.
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