CD74HCT4543E Datasheet | Texas Instruments

CD74HCT4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVER D 4.5-V to 5.5-V VCC Operation D Input Latches for BCD Code Storage D Blanking Capability D Phase Input for plementing Outputs D Fanout (Over Temperature Range) - Standard Outputs - 10 LSTTL Loads D Balanced Propagation Delay and Transition Times D Significant Power Reduction, pared to LSTTL Logic ICs D Direct LSTTL Input Logic patibility, VIL = 0.8 V Maximum, VIH = 2 V Minimum D CMOS Input patibility, II ≤ 1 µA at VOL, SCHS281A - REVISED MAY 2003 E PACKAGE (TOP VIEW) LD 1 D2 2 BCD Inputs D1 3 D3 4 D0 5 PH 6 BI 7 GND 8 16 VCC 15 f 14 g 13 e 12 d 11 c 7-Segment Outputs 10 b 9a DISPLAY 0 1 23 4 567 8 9 a fg...