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CD74HCT640 Datasheet Preview

CD74HCT640 Datasheet

Octal Three-State Bus Transceiver

No Preview Available !

Data sheet acquired from Harris Semiconductor
SCHS192B
January 1998 - Revised May 2003
CD54HC640, CD74HC640,
CD54HCT640, CD74HCT640
High-Speed CMOS Logic
Octal Three-State Bus Transceiver, Inverting
[ /Title
(CD74
HC640
,
CD74
HCT64
0)
/Sub-
ject
(High
Speed
CMOS
Features
Description
• Buffered Inputs
• Three-State Outputs
• Applications in Multiple-Data-Bus Architecture
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
The ’HC640 and ’HCT640 silicon-gate CMOS three-state
bidirectional inverting and non-inverting buffers are intended
for two-way asynchronous communication between data
buses. They have high drive current outputs which enable
high-speed operation when driving large bus capacitances.
These circuits possess the low power dissipation of CMOS
circuits, and have speeds comparable to low power Schottky
TTL circuits. They can drive 15 LSTTL loads. The ’HC640
and ’HCT640 are inverting buffers.
The direction of data flow (A to B, B to A) is controlled by the
DIR input.
Outputs are enabled by a low on the Output Enable input
(OE); a high OE puts these devices in the high impedance
mode.
Ordering Information
PART NUMBER
CD54HC640F3A
CD54HCT640F3A
CD74HC640E
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
Pinout
CD54HC640, CD54HCT640
(CERDIP)
CD74HC640, CD74HCT640
(PDIP, SOIC)
TOP VIEW
CD74HC640M
CD74HCT640E
CD74HCT640M
-55 to 125
-55 to 125
-55 to 125
20 Ld SOIC
20 Ld PDIP
20 Ld SOIC
DIR 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
GND 10
20 VCC
19 OE
18 B0
17 B1
16 B2
15 B3
14 B4
13 B5
12 B6
11 B7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1




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CD74HCT640 Datasheet Preview

CD74HCT640 Datasheet

Octal Three-State Bus Transceiver

No Preview Available !

CD54HC640, CD74HC640, CD54HCT640, CD74HCT640
Functional Diagram
A0 B0
A1
THRU
A6
B1
THRU
B6
A7 B7
OE OUTPUT ENABLE AND
DIR
DIRECTION-SELECT LOGIC
VCC = 20
GND = 10
TRUTH TABLE
CONTROL INPUTS
DATA PORT STATUS
OE DIR An Bn
L LO I
HHZ Z
HLZZ
LH I O
To prevent excess currents in the High-Z modes all I/O terminals
should be terminated with 1kto 1Mresistors.
H = High Level
L = Low Level
I = Input
O = Output (Inversion of Input Level)
Z = High Impedance
2


Part Number CD74HCT640
Description Octal Three-State Bus Transceiver
Maker etcTI
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CD74HCT640 Datasheet PDF






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