1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
D Low-Output Skew for Clock-Distribution
D Differential Low-Voltage Pseudo-ECL
(LVPECL)-Compatible Inputs and Outputs
D Distributes Differential Clock Inputs to Nine
Differential Clock Outputs
D Output Reference Voltage, VREF , Allows
Distribution From a Single-Ended Clock
D Single-Ended LVPECL-Compatible Output
D Packaged in Plastic Chip Carrier
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
4 3 2 1 28 27 26
12 13 14 15 16 17 18
The differential LVPECL clock-driver circuit
distributes one pair of differential LVPECL clock
inputs (CLKIN, CLKIN) to nine pairs of differential
clock (Y, Y) outputs with minimum skew for clock
distribution. It is specifically designed for driving
50-Ω transmission lines.
NC – No internal connection
When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential
clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state,
Y outputs are in the high state).
The VREF output can be strapped to the CLKIN input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C.
CLKIN CLKIN OE
X X H LH
L H L LH
H L L HL
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PRODUCTION DATA information is current as of publication date.
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