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CY54FCT273T - 8-BIT REGISTERS

General Description

The ’FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered-clock (CP) and master-reset (MR) inputs load and reset all flip-flops simultaneously.

These devices are edge-triggered registers.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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D Function, Pinout, and Drive Compatible With FCT and F Logic D Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions D Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics D Ioff Supports Partial-Power-Down Mode Operation D Matched Rise and Fall Times D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D Fully Compatible With TTL Input and Output Logic Levels D CY54FCT273T – 32-mA Output Sink Current – 12-mA Output Source Current D CY74FCT273T – 64-mA Output Sink Current – 32-mA Output Source Current description The ’FCT273T devices consist of eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.