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CY74FCT16501T - 18-Bit Registered Transceivers

General Description

These 18-bit universal bus transceivers can be operated in transparent, latched or clock modes by combining D-type latches and D-type flip-flops.

Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA).

Key Features

  • Ioff supports partial-power-down mode operation.
  • Edge-rate control circuitry for significantly improved noise characteristics.
  • Typical output skew < 250 ps.
  • ESD > 2000V.
  • TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages.
  • Industrial temperature range of.
  • 40˚C to +85˚C.
  • VCC = 5V ± 10% CY74FCT16501T Features:.
  • 64 mA sink current, 32 mA source current.
  • Typical VOLP (ground bounce).

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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1CY74FCT162H501 T Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16501T CY74FCT162501T CY74FCT162H501T SCCS057B - August 1994 - Revised September 2001 18-Bit Registered Transceivers Features • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6 mil pitch) and SSOP (25-mil pitch) packages • Industrial temperature range of −40˚C to +85˚C • VCC = 5V ± 10% CY74FCT16501T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.