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DP83822HF Datasheet Preview

DP83822HF Datasheet

low power 10/100 Mbps ethernet physical layer transceiver

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DP83822HF, DP83822IF, DP83822H, DP83822I
SNLS505E – AUGUST 2016 – REVISED MARCH 2019
DP83822 Robust, low power 10/100 Mbps ethernet physical layer transceiver
1 Features
1 IEEE 802.3u compliant: 100BASE-FX, 100BASE-
TX and 10BASE-Te
• MII / RMII / RGMII MAC interfaces
• Low power single supply options:
– 1.8-V AVD < 120 mW
– 3.3-V AVD < 220 mW
• ±16-kV HBM ESD protection
• ±8-kV IEC 61000-4-2 ESD protection
• Start of frame detect for IEEE 1588 time stamp
• Fast link-down timing
• Auto-crossover in force modes
• Operating temperature: –40°C to +125°C
• I/O voltages: 3.3 V, 2.5 V, and 1.8 V
• Power savings features
– Energy efficient ethernet (EEE) IEEE 802.3az
– WoL (Wake-on-LAN) support with magic
packet detection
– Programmable energy savings modes
• Cable diagnostics
• BIST (Built-In Self-Test)
• MDC / MDIO interface
2 Applications
• Industrial networks and factory automation
• Motor and motion control
• IP network cameras
• Building automation
3 Description
The DP83822 is a low power single-port 10/100 Mbps
Ethernet PHY. It provides all physical layer functions
needed to transmit and receive data over both
standard twisted-pair cables or connect to an external
fiber optic transceiver. Additionally, the DP83822
provides flexibility to connect to a MAC through a
standard MII, RMII, or RGMII interface.
The DP83822 offers integrated cable diagnostic tools,
built-in self-test, and loopback capabilities for ease of
use. It supports multiple industrial buses with its fast
link-down timing as well as Auto-MDIX in forced
modes.
The DP83822 offers an innovative and robust
approach for reducing power consumption through
EEE, WoL and other programmable energy savings
modes.
The DP83822 is a feature rich and pin-to-pin
upgradeable option for the TLK105, TLK106,
TLK105L and TLK106L 10/100 Mbps Ethernet PHYs.
The DP83822 comes in a 32-pin 5.00-mm × 5.00-mm
VQFN package.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DP83822HF
VQFN (32)
5.00 mm × 5.00 mm
DP83822H
VQFN (32)
5.00 mm × 5.00 mm
DP83822IF
VQFN (32)
5.00 mm × 5.00 mm
DP83822I
VQFN (32)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
100BASE-FX
MII
RMII
RGMII
MAC
DP83822
10/100 Mbps
Ethernet PHY
10BASE-Te
100BASE-TX
RJ-45
25-MHz / 50-MHz
Clock Source
Status
LEDs
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




etcTI

DP83822HF Datasheet Preview

DP83822HF Datasheet

low power 10/100 Mbps ethernet physical layer transceiver

No Preview Available !

DP83822HF, DP83822IF, DP83822H, DP83822I
SNLS505E – AUGUST 2016 – REVISED MARCH 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 4
6.1 IO Pins State During Reset....................................... 8
7 Specifications......................................................... 9
7.1 Absolute Maximum Ratings ...................................... 9
7.2 ESD Ratings.............................................................. 9
7.3 Recommended Operating Conditions....................... 9
7.4 Thermal Information ................................................ 10
7.5 Electrical Characteristics......................................... 10
7.6 Timing Requirements, Power-Up Timing ................ 11
7.7 Timing Requirements, Reset Timing....................... 11
7.8 Timing Requirements, Serial Management Timing. 11
7.9 Timing Requirements, 100 Mbps MII Transmit
Timing ...................................................................... 12
7.10 Timing Requirements, 100 Mbps MII Receive
Timing ...................................................................... 12
7.11 Timing Requirements, 10 Mbps MII Transmit
Timing ...................................................................... 12
7.12 Timing Requirements, 10 Mbps MII Receive
Timing ...................................................................... 12
7.13 Timing Requirements, RMII Transmit Timing ....... 13
7.14 Timing Requirements, RMII Receive Timing ........ 13
7.15 Timing Requirements, RGMII ............................... 13
7.16 Normal Link Pulse Timing ..................................... 14
7.17 Auto-Negotiation Fast Link Pulse (FLP) Timing.... 14
7.18 10BASE-Te Jabber Timing ................................... 14
7.19 MII: 100BASE-TX Transmit Latency Timing ......... 14
7.20 MII: 100BASE-TX Receive Latency Timing .......... 14
7.21 Timing Diagrams ................................................... 15
7.22 Typical Characteristics .......................................... 23
8 Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 25
8.3 Feature Description................................................. 26
8.4 Device Functional Modes........................................ 29
8.5 Programming .......................................................... 46
8.6 Register Maps ......................................................... 51
9 Application and Implementation ........................ 91
9.1 Application Information............................................ 91
9.2 Typical Applications ............................................... 91
10 Power Supply Recommendations ..................... 97
10.1 Power Supply Characteristics ............................... 97
11 Layout................................................................. 102
11.1 Layout Guidelines ............................................... 102
11.2 Layout Example .................................................. 105
12 Device and Documentation Support ............... 106
12.1 Related Links ...................................................... 106
12.2 Receiving Notification of Documentation
Updates.................................................................. 106
12.3 Community Resources........................................ 106
12.4 Trademarks ......................................................... 106
12.5 Electrostatic Discharge Caution .......................... 106
12.6 Glossary .............................................................. 106
13 Mechanical, Packaging, and Orderable
Information ......................................................... 106
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2019) to Revision E
Page
• Changed to fix typos on Table 1 ........................................................................................................................................... 8
Changes from Revision C (April 2018) to Revision D
Page
• Changed the description for LED_1 in Pin Functions table.................................................................................................... 6
• Changed reset pin state for RX_D[3:0] pins in Table 1.......................................................................................................... 8
• Added XO and XI capacitance ............................................................................................................................................. 10
• Added Test Conditions to PMD OUTPUT section of the Electrical Characteristics Table ................................................... 11
• Changed Parameter descriptions and units in Reset Timing Requirements table to match device performance. .............. 11
• Changed NOTE for 100BASE-FX Signal Detect pin polarity from Active LOW to Active HIGH. ......................................... 40
• Changed LED_0 strap modes to remove Mode 2 and Mode 3. .......................................................................................... 48
• Changed strap description for SD_EN pin from Active LOW to Active HIGH. ..................................................................... 48
• Deleted LED_0 configuration table....................................................................................................................................... 49
• Changed LED_1 Configuration table to merge LED_0 and LED_1 configuration into a single table for clarity. ................. 49
• Changed note in LED Configuration section to clarify LED connections. ............................................................................ 50
• Added registers 0x0106, 0x0107, 0x01F, 0x0114, 0x0116, 0x0126, 0x04D4, 0x04D5, and 0x04D6 ................................. 51
2 Submit Documentation Feedback
Copyright © 2016–2019, Texas Instruments Incorporated
Product Folder Links: DP83822HF DP83822IF DP83822H DP83822I


Part Number DP83822HF
Description low power 10/100 Mbps ethernet physical layer transceiver
Maker etcTI
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