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DS26LV32AQML Datasheet Preview

DS26LV32AQML Datasheet

3V Enhanced CMOS Quad Differential Line Receiver

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DS26LV32AQML
www.ti.com
SNOSAS7A – MARCH 2006 – REVISED APRIL 2013
DS26LV32AQML 3V Enhanced CMOS Quad Differential Line Receiver
Check for Samples: DS26LV32AQML
FEATURES
1
2 Comparable to Both TIA/EIA-422 and ITU-T
V.11 Standards
• Low Power CMOS Design (30 mW typical)
• Interoperable with Existing 5V RS-422
Networks
• Receiver OPEN Input Failsafe Feature
• Pin Compatible with DS26C32AT
DESCRIPTION
The DS26LV32A is a high speed quad differential
CMOS receiver that is comparable to TIA/EIA-422-B
and ITU-T V.11 standards, but with a specified
common mode voltage range of -0.5V to +5.5V due
to the lower operating supply voltage of 3.0V to 3.6V.
The TRI-STATE enables, EN and EN, allow the
device to be active High or active Low. The enables
are common to all four receivers. The receiver output
(RO) is specified to be High when the inputs are left
open. The receiver can detect signals as low as
±200mV over the common mode range of -0.5V to
+5.5V. The receiver outputs (RO) are compatible with
TTL and LVCMOS levels.
Connection Diagram
Figure 1. CLGA Package- Top View
See Package Number NAD0016A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated




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DS26LV32AQML Datasheet Preview

DS26LV32AQML Datasheet

3V Enhanced CMOS Quad Differential Line Receiver

No Preview Available !

DS26LV32AQML
SNOSAS7A – MARCH 2006 – REVISED APRIL 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage (VCC)
Common Mode Range (VCM)
Differential Input Voltage (VDiff)
Enable Input Voltage (VI)
Storage Temperature Range (TStg)
Lead Temperature (TL) Soldering, 4 seconds
Maximum Power Dissipation +25°C (2)
7.0V
±14V
±14V
-0.5V to VCC+0.5V
-65°C TA +150°C
260°C
1087mW
Thermal Resistance
θJA
138°C/W
θJC
13.5°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not verify specific performance limits. For verified specifications and test conditions, see the
Electrical Characteristics. The verified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) Derate CERPAK 7.3mW/°C above +25°C.
Recommended Operating Conditions
Supply Voltage (vCC)
Operating Temperature Range (TA)
3.0V to 3.6V
55°C TA +125°C
Table 1. Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A
Subgroup
1
2
3
4
5
6
7
8A
8B
9
10
11
12
13
14
Description
Static tests at
Static tests at
Static tests at
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Settling time at
Settling time at
Settling time at
Temp °C
25
125
-55
25
125
-55
25
125
-55
25
125
-55
25
125
-55
2
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: DS26LV32AQML


Part Number DS26LV32AQML
Description 3V Enhanced CMOS Quad Differential Line Receiver
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