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DS90LV018A 3V LVDS Single CMOS Differential Line Receiver

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Description

DS90LV018A www.ti.com SNLS014D * JUNE 1998 * REVISED APRIL 2013 DS90LV018A 3V LVDS Single CMOS Differential Line Receiver Check for.
The DS90LV018A is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise and high data ra.

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Features

* 1
* 2 >400 Mbps (200 MHz) Switching Rates
* 50 ps Differential Skew (Typical)
* 2.5 ns Maximum Propagation Delay
* 3.3V Power Supply Design
* Flow-Through Pinout
* Power Down High Impedance on LVDS Inputs
* Low Power Design (18mW @ 3.3V Static)

Applications

* requiring ultra low power dissipation, low noise and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV018A accepts low voltage (350 mV typical) differential input signals and transl

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