* 1 >400 Mbps (200 MHz) Switching Rates
* 0.1-ns Channel-to-Channel Skew (Typical)
* 0.1-ns Differential Skew (Typical)
* 3.3-ns Maximum Propagation Delay
* 3.3-V Power Supply Design
* Power Down High Impedance on LVDS Inputs
* Low Power Design
DS90LV032A Datasheet (697.01 KB)
DS90LV032A
697.01 KB
3-v lvds quad cmos differential line receiver.
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DS90LV032A SNLS011D JULY 1999 REVISED AU.
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