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DS90UB948-Q1 Datasheet Preview

DS90UB948-Q1 Datasheet

2K FPD-Link3 to OpenLDI Deserializer

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DS90UB948-Q1
SNLS477B – OCTOBER 2014 – REVISED NOVEMBER 2018
DS90UB948-Q1 2K FPD-Link III to OpenLDI Deserializer
1 Features
1 Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
• Supports Pixel Clock Frequency up to 192 MHz
for up to 2K (2048x1080) Resolutions With 24-Bit
Color Depth
• 1-Lane or 2-Lane FPD-Link III Interface With De-
Skew Capability
• Single or Dual OpenLDI (LVDS) Transmitter
– Single Channel: Up to 96-MHz Pixel Clock
– Dual Channel: Up to 192-MHz Pixel Clock
– Configurable 18-Bit RGB or 24-Bit RGB
• Four High-Speed GPIOs (up to 2 Mbps each)
• Adaptive Receive Equalization
– Compensates for Channel Insertion Loss of up
to –15.3 dB at 1.7 GHz
– Provides Automatic Temperature and Cable
Aging Compensation
• SPI Control Interfaces up to 3.3 Mbps
• I2C (Master/Slave) With 1-Mbps Fast-Mode Plus
• Image Enhancement (White Balance and
Dithering)
• Supports 7.1 Multiple I2S (4 Data) Channels
2 Applications
• Automotive Infotainment:
– Central Information Displays
– Rear Seat Entertainment Systems
– Digital Instrument Clusters
3 Description
The DS90UB948-Q1 is a FPD-Link III deserializer
which, in conjunction with the DS90UB949A/949/947-
Q1 serializers, converts 1-lane or 2-lane FPD-Link III
streams into a FPD-Link (OpenLDI) interface. The
Deserializer is capable of operating over cost-
effective 50-Ω single-ended coaxial or 100-Ω
differential shielded twisted-pair (STP) cables. It
recovers the data from one or two FPD-Link III serial
streams and translates it into dual pixel FPD-Link (8
LVDS data lanes + clock) supporting video
resolutions up to 2K (2048x1080) with 24-bit color
depth. This provides a bridge between HDMI enabled
sources such as GPUs to connect to existing LVDS
displays or application processors.
The FPD-Link III interface supports video and audio
data transmission and full duplex control, including
I2C and SPI communication, over the same
differential link. Consolidation of video data and
control over two differential pairs decreases the
interconnect size and weight and simplifies system
design. EMI is minimized by the use of low voltage
differential signaling, data scrambling, and
randomization. In backward compatible mode, the
device supports up to WXGA and 720p resolutions
with 24-bit color depth over a single differential link.
The device automatically senses the FPD-Link III
channels and supplies a clock alignment and de-skew
functionality without the need for any special training
patterns. This ensures skew phase tolerance from
mismatches in interconnect wires such as PCB trace
routing, cable pair-to-pair length differences, and
connector imbalances.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UB948-Q1
WQFN (64)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Mobile
Device
or
Graphics
Processor
HDMI
or
DP++
IN_CLK-/+
IN_D0-/+
IN_D1-/+
IN_D2-/+
CEC
DDC
HPD
I2C
IDx
HS_GPIO
(SPI)
Figure 1. Typical Application
DOUT0+
DOUT0-
DOUT1+
DOUT1-
DS90UB949-Q1
Serializer
FPD-Link III
2 lanes
RIN0+
RIN0-
RIN1+
RIN1-
DS90UB948-Q1
Deserializer
FPD-Link
Open LDI
D3±
D2±
D1±
D0±
CLK1±
D4±
D5±
D6±
D7±
CLK2±
Display
or
Graphics
Processor
I2C
IDx
HS_GPIO
(SPI)
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




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DS90UB948-Q1 Datasheet Preview

DS90UB948-Q1 Datasheet

2K FPD-Link3 to OpenLDI Deserializer

No Preview Available !

DS90UB948-Q1
SNLS477B – OCTOBER 2014 – REVISED NOVEMBER 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 5
6 Specifications....................................................... 11
6.1 Absolute Maximum Ratings .................................... 11
6.2 ESD Ratings............................................................ 11
6.3 Recommended Operating Conditions..................... 11
6.4 Thermal Information ................................................ 12
6.5 DC Electrical Characteristics .................................. 12
6.6 AC Electrical Characteristics................................... 15
6.7 Timing Requirements for the Serial Control Bus .... 16
6.8 Switching Characteristics ........................................ 17
6.9 Timing Diagrams and Test Circuits......................... 18
6.10 Typical Characteristics .......................................... 21
7 Detailed Description ............................................ 22
7.1 Overview ................................................................. 22
7.2 Functional Block Diagram ....................................... 22
7.3 Feature Description................................................. 23
7.4 Device Functional Modes........................................ 40
7.5 Image Enhancement Features................................ 48
7.6 Programming........................................................... 51
7.7 Register Maps ......................................................... 54
8 Application and Implementation ........................ 85
8.1 Application Information ......................................... 85
8.2 Typical Applications ................................................ 85
9 Power Supply Recommendations...................... 90
9.1 Power-Up Requirements and PDB Pin ................... 90
9.2 Power Sequence..................................................... 91
10 Layout................................................................... 93
10.1 Layout Guidelines ................................................. 93
10.2 Ground .................................................................. 93
10.3 Routing FPD-Link III Signal Traces ..................... 93
10.4 Layout Example .................................................... 95
11 Device and Documentation Support ................. 97
11.1 Documentation Support ....................................... 97
11.2 Receiving Notification of Documentation Updates 97
11.3 Community Resources.......................................... 97
11.4 Trademarks ........................................................... 97
11.5 Electrostatic Discharge Caution ............................ 97
11.6 Glossary ................................................................ 97
12 Mechanical, Packaging, and Orderable
Information ........................................................... 98
4 Revision History
Changes from Revision A (January 2016) to Revision B
Page
• Changed PCLK frequency to support higher speed 192 MHz. ............................................................................................. 1
• Changed "1.2 V" to "1.25 V" at top of DS90Ux940 Deserializer in Typ App.......................................................................... 1
• Simplified the typical application by removing the power supplies nodes. ............................................................................ 1
• Removed bolded pin description name for power supplies. .................................................................................................. 5
• Added new pin description content to the Pin Functions table ............................................................................................. 5
• Changed the description from VDDIO to V(I2C). .................................................................................................................. 6
• Specified in current instead of resistor for all pulldown resistor ............................................................................................ 6
• Removed 200-µA minimum ramp time for PDB pin description. ........................................................................................... 7
• Added the description to clarify the INTB_IN that this pin can be an output driver................................................................ 7
• Changed pin names from CAP_PLL0 and CAP_PLL1 to RES0 and RES1 respectively. .................................................... 9
• Removed tablenote from the Absolute Maximum Ratings table: For soldering specifications, see product folder at
www.ti.com and SNOA549 .................................................................................................................................................. 11
• Added Military/Aerospace tablenote to the Absolute Maximum Ratings table .................................................................... 11
• Changed supply voltage maximum for the VDD33 from: 4 V to: 3.96 V ............................................................................. 11
• Changed VDD12 abs max from 1.8V to 1.44V. .................................................................................................................. 11
• Changed supply voltage for the VDDIO from: 4 V to: 3.96 V .............................................................................................. 11
• Added the Added the open-drain voltage, CML output voltage, and FPD-Link III input voltage parameters to the
Absolute Maximum Ratings table , open-drain voltage, CML output voltage, and FPD-Link III input voltage
parameters to the Absolute Maximum Ratings table ........................................................................................................... 11
• Added test conditions to the LVCMOS I/O voltage parameter ............................................................................................ 11
• Spelled out all GPIOs pin name. .......................................................................................................................................... 11
• Combined the ESD ratings into one ESD Ratings table ..................................................................................................... 11
• Removed VDD18 test condition from the supply voltage parameter .................................................................................. 11
2 Submit Documentation Feedback
Copyright © 2014–2018, Texas Instruments Incorporated
Product Folder Links: DS90UB948-Q1


Part Number DS90UB948-Q1
Description 2K FPD-Link3 to OpenLDI Deserializer
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