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DS99R104 - 3-40MHz DC-Balanced 24-Bit LVDS Serializer / Deserializer

Download the DS99R104 datasheet PDF. This datasheet also covers the DS99R103 variant, as both devices belong to the same 3-40mhz dc-balanced 24-bit lvds serializer / deserializer family and are provided as variant models within a single manufacturer datasheet.

General Description

The DS99R103/DS99R104 Chipset translates a 24bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Key Features

  • 1.
  • 2 3 MHz.
  • 40 MHz Clock Embedded and DCBalancing 24:1 and 1:24 Data Transmissions.
  • Capable to Drive Shielded Twisted-Pair Cable.
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver.
  • Internal DC Balancing Encode/Decode.
  • Supports AC-Coupling Interface with no External Coding Required.
  • Individual Power-Down Controls for both Transmitter and Receiver.
  • Embedded Clock CDR (Clock and Data Recovery) on Receiv.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS99R103-etcTI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for DS99R104 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DS99R104. For precise diagrams, and layout, please refer to the original PDF.

DS99R103, DS99R104 www.ti....

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