HC595M
description
/ordering information
DW, E, M, NS, OR SM PACKAGE (TOP VIEW)
QB 1 QC 2 QD 3 QE 4 QF 5 QG 6 QH 7 GND 8
16 VCC 15 QA 14 SER 13 OE 12 RCLK 11 SRCLK 10 SRCLR 9 QH′
The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial output for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
ORDERING INFORMATION
PACKAGE†
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PDIP
- E
Tube of 25
CD74HC595E
CD74HC595E
SOIC
- DW
Tube of 40 Reel of...
