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LM2512A Datasheet Preview

LM2512A Datasheet

24-Bit RGB Display Interface Serializer

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LM2512A
www.ti.com
SNLS269B – AUGUST 2007 – REVISED MAY 2013
LM2512A Mobile Pixel Link (MPL-1), 24-Bit RGB Display Interface Serializer with Optional
Dithering and Look Up Table
Check for Samples: LM2512A
FEATURES
1
2 24-bit RGB Interface Support up to 640 x 480
VGA Format
• Optional 24 to 18-bit Dithering
• Optional Look Up Table for Independent Color
Correction
• MPL-1 Physical Layer
• SPI Interface for Look Up Table Control and
Loading
• Low Power Consumption & Powerdown State
• Level Translation Between Host and Display
• Optional Auto Power Down on STOP PCLK
• Frame Sequence Bits Auto Resync upon Data
or Clock Error
• 1.6V to 2.0V Core / Analog Supply Voltage
• 1.6V to 3.0V I/O Supply Voltage Range
SYSTEM BENEFITS
• Dithered Data Reduction
• Independent RGB Color Correction
• 24-bit Color Input
• Small Interface, Low Power and Low EMI
• Intrinsic Level Translation
DESCRIPTION
The LM2512A is a MPL Serializer (SER) that
performs a 24-bit to 18-bit Dither operation and
serialization of the video signals to Mobile Pixel link
(MPL) levels on only 3 or 4 active signals. An optional
Look Up Table (Three X 256 X 8 bit RAM) is also
provided for independent color correction. 18-bit
Bufferless or partial buffer displays from QVGA (320
x 240) up to VGA (640 x 480) pixels can utilize a 24-
bit video source.
The interconnect is reduced from 28 signals to only 3
or 4 active signals with the LM2512A and companion
deserializer easing flex interconnect design, size
constraints and cost.
The LM2512A SER resides by the application,
graphics or baseband processor and translates the
wide parallel video bus from LVCMOS levels to serial
Mobile Pixel Link levels for transmission over a flex
cable (or coax) and PCB traces to the DES located
near or in the display module.
When in Power_Down, the SER is put to sleep and
draws less than 10μA. The link can also be powered
down by stopping the PCLK (DES dependant) or by
the PD* input pins.
The LM2512A provides enhanced AC performance
over the LM2512. It implements the physical layer of
the MPL-1 and uses a single-ended current-mode
transmission.
Typical 3 MD Lane Application Diagram - Bridge Chip
Apps
Processor
---
Graphics
Processor
---
Baseband
Processor
R[7:0]
G[7:0]
B[7:0]
VS
HS
DE
PCLK
LM2512A Serializer
D
iP
t2
hS
e
r
MD0
MD1
MC
MPL-1 Deserializer
R[5:0]
G[5:0]
B[5:0]
VS
HS
DE
PCLK
SPI_CSX
S Three
P 256 X
SPI_SCL
I
8
SPI_SDA
LUT
PD*
MD2
PLL
RGB Display
VGA
at 18-Bit Color Depth
[Supply, Configuration pins,
and bypass caps. and grounding not shown]
PD*
PDOUT*
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated




etcTI

LM2512A Datasheet Preview

LM2512A Datasheet

24-Bit RGB Display Interface Serializer

No Preview Available !

LM2512A
SNLS269B – AUGUST 2007 – REVISED MAY 2013
www.ti.com
Pin Name
No.
of Pins
I/O, Type(1)
MPL SERIAL BUS PINS
MD[2:0]
3
O, MPL
MC
1
O, MPL
SPI INTERFACE and CONFIGURATION PINS
SPI_CSX
1
I,
LVCMOS
SPI_SCL
1
I,
LVCMOS
SPI_SDA/HS
1
IO,
LVCMOS
PD*
1
I,
LVCMOS
RES1
1
TM
1
NC
1
VIDEO INTERFACE PINS
PCLK
1
R[7:0]
24
G[7:0]
B[7:0]
VS
1
SPI_SDA/HS
1
DE
1
POWER/GROUND PINS
VDDA
1
VDD
1
VDDIO
3
VSSA
1
VSS
1
VSSIO
4
I,
LVCMOS
I,
LVCMOS
NA
I,
LVCMOS
I,
LVCMOS
I,
LVCMOS
IO,
LVCMOS
I,
LVCMOS
Power
Power
Power
Ground
Ground
Ground
Pin Descriptions
Description
RGB Serializer
MPL Data Line Driver
MPL Clock Line Driver
SPI_Chip Select Input
SPI port is enabled when: SPI_CSX is Low, PD* is High, and PCLK is static.
SPI_Clock Input
Multi-function Pin:
If SPI_CSX is Low, this is the SPI_SDA IO signal. Default is Input. Pin will be an
output for a SPI Read transaction.
See HS description below also.
Power Down Mode Input
SER is in sleep mode when PD* = Low, SER is enabled when PD* = High
In PD*=L - Sleep mode: SPI interface is OFF, Register settings are RESET, and
LUT data is retained.
Reserved 1 - Tie High (VDDIO) only available on NZK0049A package
Test Mode
L = Normal Mode, tie to GND
H = Test Mode (Reserved)
Not Connected - Leave Open; only on NZK0049A package
Pixel Clock Input
Video Signals are latched on the RISING edge.
RGB Data Bus Inputs – Bit 7 is the MSB.
Vertical Sync. Input
This signal is used as a frame start for the Dither block and is required. The
VS signal is serialized unmodified.
Multi-function Pin:
Horizontal Sync. Input (when SPI_CSX = High)
See SPI_SDA description above also.
Data Enable Input
Power Supply Pin for the PLL (SER) and MPL Interface.
1.6V to 2.0V
Power Supply Pin for the digital core.
1.6V to 2.0V
Power Supply Pin for the parallel interface I/Os.
1.6V to 3.0V
Ground Pin for PLL (SER) and MPL interface
Ground Pin for digital core. For SN40A package, this is the large center pad.
Ground Pin for the parallel interface I/Os. For NJM0040A package, this is the large
center pad.
(1) Note: I = Input, O = Output, IO = Input/Output. Do not float input pins.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Submit Documentation Feedback
Product Folder Links: LM2512A
Copyright © 2007–2013, Texas Instruments Incorporated


Part Number LM2512A
Description 24-Bit RGB Display Interface Serializer
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LM2512A Datasheet PDF






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