Datasheet Summary
.ti.
LMK04000, LMK04001, LMK04002, LMK04010 LMK04011, LMK04031, LMK04033
SNOSAZ8J
- SEPTEMBER 2008
- REVISED SEPTEMBER 2011
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Check for Samples: LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033
Features
- 23 Cascaded PLLatinum™ PLL Architecture
- PLL1
- Phase Detector Rate of up to 40 MHz
- Integrated Low-Noise Crystal Oscillator Circuit
- Dual Redundant Input Reference Clock with LOS
- PLL2
- Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz
- Phase Detector Rate up to 100 MHz
- Input Frequency-Doubler
- Integrated Low-Noise VCO
- Ultra-Low RMS Jitter Performance
- 150 fs RMS Jitter (12 kHz
- 20...
