Texas Instruments LMK04010
The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a lownoise jitter cleaner function while the second PLL (PLL2) performs the clock generation.| Part No. | LMK04010 |
|---|---|
| Datasheet | LMK04010 Download |
| Manufacturer |  Texas Instruments |
| Description | Family Low-Noise Clock Jitter Cleaner |
| Buy | Stock & Price |
FEATURES
1●23 Cascaded PLLatinum™ PLL Architecture – PLL1 – Phase Detector Rate of up to 40 MHz – Integrated Low-Noise Crystal Oscillator Circuit – Dual Redundant Input Reference Clock with LOS – PLL2 – Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated Low-Noise VCO
● Ultra-Low RMS Jitter Performance – 150 fs RMS Jitter (12 kHz – 20 MHz) – 200 fs RMS Jitter (100 Hz – 20 MHz)
● LVPECL/2VPECL, LVDS, and LVCMOS outputs
● Support Clock Rates up to 1080 MHz
● Default Clock Output (CLKout2) at power up
● Five Dedicated Channel Divider and Delay Blocks
● Pin Compatible Family of Clocking Devices
● Industrial Temperature Range: -40 to 85 °C
● 3.15 V to 3.45 V Operation
● Package: 48 Pin WQFN (7.0 x 7.0 x 0.8 mm)
APPLICATIONS
● Data Converter Clocking● Wireless Infrastructure
● Networking, SONET/SDH, DSLAM
● Medical
● Military / Aerospace
● Test and Measurement
● Video
DESCRIPTION
Using a cascaded PLLatinum™ architecture...
