* One Digital Phase-Locked Loop (DPLL) With:
* Hitless Switching: ±50-ps Phase Transient
* Programmable Loop Bandwidth With Fastlock
* Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO
* Two Analog Phase-Locked Loops (APLLs) With Indu
LMK5B12204 Datasheet (4.72 MB)
LMK5B12204
4.72 MB
Ultra-low jitter network synchronizer clock.
www.ti.com LMK5B12204 SNAS810A MAY 2020 REVISEDLMJAKNU5ABR1Y22200241 SNAS810A MAY 2020 REVISED JANUARY 2021 .
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