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LP2997 Datasheet Preview

LP2997 Datasheet

DDR-II Termination Regulator

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LP2997
www.ti.com
SNVS295F – MAY 2004 – REVISED APRIL 2013
LP2997 DDR-II Termination Regulator
Check for Samples: LP2997
FEATURES
1
2 Source and Sink Current
• Low Output Voltage Offset
• No External Resistors Required
• Linear Topology
• Suspend to Ram (STR) Functionality
• Low External Component Count
• Thermal Shutdown
• Available in SOIC-8, SO PowerPAD-8 Packages
APPLICATIONS
• DDR-II Termination Voltage
• SSTL-18 Termination
DESCRIPTION
The LP2997 linear regulator is designed to meet the
JEDEC SSTL-18 specifications for termination of
DDR-II memory. The device contains a high-speed
operational amplifier to provide excellent response to
load transients. The output stage prevents shoot
through while delivering 500mA continuous current
and transient peaks up to 900mA in the application as
required for DDR-II SDRAM termination. The LP2997
also incorporates a VSENSE pin to provide superior
load regulation and a VREF output as a reference for
the chipset and DIMMs.
An additional feature found on the LP2997 is an
active low shutdown (SD) pin that provides Suspend
To RAM (STR) functionality. When SD is pulled low
the VTT output will tri-state providing a high
impedance output, but, VREF will remain active. A
power savings advantage can be obtained in this
mode through lower quiescent current.
Typical Application Circuit
SD
AV IN = 2.5V
VDDQ = 1.8V
+
CIN
LP2997
SD
AVIN
VREF
V DDQ
V SENSE
PVIN
VTT
GND
+
CREF
VREF = 0.9V
+
C OUT
V TT= 0.9V
Figure 1. Typical Application Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated




etcTI

LP2997 Datasheet Preview

LP2997 Datasheet

DDR-II Termination Regulator

No Preview Available !

LP2997
SNVS295F – MAY 2004 – REVISED APRIL 2013
Connection Diagram
www.ti.com
GND 1
SD 2
VSENSE 3
VREF 4
GND
8 VTT
7 PVIN
6 AVIN
5 VDDQ
Figure 2. SO PowerPAD-8 Layout
See Package Number DDA (R-PDSO-G8)
GND 1
SD 2
VSENSE 3
VREF 4
8 VTT
7 PVIN
6 AVIN
5 VDDQ
Figure 3. SOIC-8 Layout
See Package Number D0008A
SOIC-8 Pin or
SO PowerPAD-8 Pin
1
2
3
4
5
6
7
8
Name
GND
SD
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
EP
PIN DESCRIPTIONS
Function
Ground
Shutdown
Feedback pin for regulating VTT.
Buffered internal reference voltage of VDDQ/2
Input for internal reference equal to VDDQ/2
Analog input pin
Power input pin
Output voltage for connection to termination resistors
Exposed pad thermal connection Connect to Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
AVIN to GND
PVIN to GND
VDDQ (3)
Storage Temp. Range
Junction Temperature
Lead Temperature (Soldering, 10 sec)
SOIC-8 Thermal Resistance (θJA)
SO PowerPAD-8 Thermal Resistance (θJA)
Minimum ESD Rating(4)
0.3V to +6V
-0.3V to AVIN
0.3V to +6V
65°C to +150°C
150°C
260°C
151°C/W
43°C/W
1kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which
the device is intended to be functional, but does not ensure specific performance limits. For specific specifications and test conditions
see Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) VDDQ voltage must be less than 2 x (AVIN - 1) or 6V, whichever is smaller.
(4) The human body model is a 100pF capacitor discharged through a 1.5kresistor into each pin.
Operating Range
Junction Temp. Range(1)
AVIN to GND
0°C to +125°C
2.2V to 5.5V
(1) At elevated temperatures, devices must be derated based on thermal resistance. The device in the SOIC-8 package must be derated at
θJA = 151.2° C/W junction to ambient with no heat sink.
2
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Product Folder Links: LP2997
Copyright © 2004–2013, Texas Instruments Incorporated


Part Number LP2997
Description DDR-II Termination Regulator
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