LSF0108 Datasheet | Texas Instruments

Features 3 Description - Provides bidirectional voltage translation with no direction pin - Supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30 p F capacitive load and up To 40-MHz up or down translation at 50 p F capacitive load - Allows bidirectional voltage-level translation between - 0.65 V ↔ 1.8/2.5/3.3/5 V - 0.95 V ↔ 1.8/2.5/3.3/5 V - 1.2 V ↔ 1.8/2.5/3.3/5 V - 1.8 V ↔ 2.5/3.3/5 V - 2.5 V ↔ 3.3/5 V - 3.3 V ↔ 5 V - Low standby current - 5-V tolerance I/O port to support TTL - Low RON provides less signal distortion - High-impedance I/O pins for EN = Low - Flow-through pinout for easy PCB trace routing - Latch-up performance >100 m A per JESD 17 - - 40°C to 125°C operating temperature range 2 Applications - GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and other interfaces in tele infrastructure - Enterprise systems - munications equipment - Personal electronics - Industrial applications Vref_A The LSF family of devices supports bidirectional voltage translation without the need for DIR pin which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100-MHz up translation and greater than 100-MHz down translation at ≤ 30 p F capacitive load and up to 40-MHz up or down translation at 50 p F capacitive load which allows the LSF family to support more consumer or tele interfaces (MDIO or SDIO). LSF family supports 5-V tolerance on I/O port which makes it patible with TTL levels in industrial and tele applications. The LSF family is able to set up different voltage translation levels on each channel which makes it very flexible. Package Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) RKS (VQFN, 20) 4.50 mm × 2.50 mm PW (TSSOP, 20) 4.40 mm × 6.50 mm DGS (VSSOP, 20) 3.00 mm × 5.10 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Vref_B 19 3...