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SM320C50-EP Datasheet Preview

SM320C50-EP Datasheet

Digital Signal Processor

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SM320C50ĆEP
DIGITAL SIGNAL PROCESSOR
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product Change Notification
D Qualification Pedigree
D Military Operating Temperature Range:
−55°C to 125°C
D Industrial Operating Temperature Range:
−40°C to 85°C
D Fast Instruction Cycle Time (30 ns and
40 ns) and 25 ns for Industrial Temp Range
D Source-Code Compatible With All
TMS320C1x and TMS320C2x Devices
D RAM-Based Operation
− 9K × 16-Bit Single-Cycle On-Chip
Program/Data RAM
− 1056 × 16-Bit Dual-Access On-Chip
Data RAM
D 2K × 16-Bit On-Chip Boot ROM
D 224K × 16-Bit Maximum Addressable
External Memory Space (64K Program,
64K Data, 64K I/O, and 32K Global)
D 32-Bit Arithmetic Logic Unit (ALU)
− 32-bit Accumulator (ACC)
− 32-Bit Accumulator Buffer (ACCB)
D 16-Bit Parallel Logic Unit (PLU)
D 16 × 16-Bit Multiplier, 32-Bit Product
D 11 Context-Switch Registers
D Two Buffers for Circular Addressing
SGUS040A − AUGUST 2002 − REVISED JANUARY 2006
17
18
PQ PACKAGE
(TOP VIEW)
1 132
117
116
50
84
51
83
D Full-Duplex Synchronous Serial Port
D Time-Division Multiplexed Serial Port (TDM)
D Timer With Control and Counter Registers
D 16 Software-Programmable Wait-State
Generators
D Divide-by-One Clock Option
D IEEE 1149.1Boundary Scan Logic
D Operations Are Fully Static
D Enhanced Performance Implanted CMOS
(EPIC) Technology Fabricated by Texas
Instruments
D Packaging
− 132-Lead Plastic Quad Flat Package
(PQ Suffix)
description
The SM320C50-EP digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.72-µm double-level metal CMOS technology. The C50 is the first DSP from TI designed as
a fully static device. Full-static CMOS design contributes to low power consumption while maintaining high
performance, making it ideal for applications such as battery-operated communications systems, satellite
systems, and advanced control algorithms.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
EEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2006, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1




etcTI

SM320C50-EP Datasheet Preview

SM320C50-EP Datasheet

Digital Signal Processor

No Preview Available !

SM320C50ĆEP
DIGITAL SIGNAL PROCESSOR
SGUS040A − AUGUST 2002 − REVISED JANUARY 2006
description (continued)
A number of enhancements to the basic C2x architecture give the C50 a minimum 2× performance over the
previous generation. A four-deep instruction pipeline, that incorporates delayed branching, delayed call to
subroutine, and delayed return from subroutine, allows the C50 to perform instructions in fewer cycles. The
addition of a parallel logic unit (PLU) gives the C50 a method for manipulating bits in data memory without using
the accumulator and ALU. The C50 has additional shifting and scaling capability for proper alignment of
multiplicands or storage of values to data memory.
The C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional
clock from the internal hardware of the C50, which puts it into a total-sleep mode that uses only 7 µA. A low-logic
level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.
The SM320C50-EP is available with a clock speed of 66 MHz providing a 30-ns cycle time and a clock speed
of 80 MHz providing a 25-ns cycle time. The available options are listed in Table 1.
PART NUMBER
SM320C50PQM66EP
SM320C50PQI80EP
Table 1. Available Options
SPEED
30 ns cycle time
25 ns cycle time
SUPPLY
VOLTAGE
TOLERANCE
±5%
±5%
PACKAGE
Plastic Quad flat package
Plastic Quad flat package
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443



Part Number SM320C50-EP
Description Digital Signal Processor
Maker etcTI
Total Page 3 Pages
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