SM320C6711-EP
Features
- Hardware Support for IEEE Single-Precision and Double-Precision Instructions
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
D Device Configuration
- Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
- Endianness: Little Endian, Big Endian
SGUS054A
- AUGUST 2004
- REVISED SEPTEMBER 2005
D L1/L2 Memory Architecture
- 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
- 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
- 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
D Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D 32-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- 256M-Byte Total Addressable External Memory Space
D 16-Bit Host-Port Interface (HPI) D Two Multichannel Buffered Serial Ports
(Mc BSPs)
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