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SM320C80 Datasheet Preview

SM320C80 Datasheet

Digital Signal Processor

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D Single-Chip Parallel Multiple
Instruction/Multiple Data (MIMD) Digital
Signal Processor (DSP)
D More Than Two Billion RISC-Equivalent
Operations per Second
D Master Processor (MP)
-- 32-Bit Reduced Instruction Set
Computing (RISC) Processor
-- IEEE-754 Floating-Point Capability
-- 4K-Byte Instruction Cache
-- 4K-Byte Data Cache
D Four Parallel Processors (PP)
-- 32-Bit Advanced DSPs
-- 64-Bit Opcode Provides Many Parallel
Operations per Cycle
-- 2K-Byte Instruction Cache and 8K-Byte
Data RAM per PP
D Transfer Controller (TC)
-- 64-Bit Data Transfers
-- Up to 400 Megabytes per Second (MBps)
Transfer Rate
-- 32-Bit Addressing
-- Direct DRAM/VRAM Interface With
Dynamic Bus Sizing
-- Intelligent Queuing and Cycle
Prioritization
D Video Controller (VC)
-- Provides Video Timing and Video
Random-Access Memory (VRAM)
Control
-- Dual-Frame Timers for Two Simultaneous
Image-Capture and/or Display Systems
D Big- or Little-Endian Operation
D 50K-Byte On-Chip RAM
D 4G-Byte Address Space
D 20-ns Cycle Time
D 3.3-V Operation
D IEEE Standard 1149.1Test Access Port
(JTAG)
D Operating Temperature Range
--55°C to 125°C - M-Temperature
--40°C to 85°C - A-Temperature
SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B -- AUGUST 1998 -- REVISED JUNE 2002
GF PACKAGE
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320
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IEEE Standard 1149.1--1990, IEEE Standard Test Access Port and Boundary-Scan Architecture
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
1




etcTI

SM320C80 Datasheet Preview

SM320C80 Datasheet

Digital Signal Processor

No Preview Available !

SMJ320C80
DIGITAL SIGNAL PROCESSOR
SGUS025B -- AUGUST 1998 -- REVISED JUNE 2002
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
GF Pin Assignments -- Numerical Listing . . . . . . . . . . . . . . . 3
GF Pin Assignments -- Alphabetical Listing . . . . . . . . . . . . . . 5
HFH Pin Assignments -- Numerical Listing . . . . . . . . . . . . . . 7
HFH Pin Assignments -- Alphabetical Listing . . . . . . . . . . . . 9
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
master processor (MP) architecture . . . . . . . . . . . . . . . . . . . 17
MP control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MP interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PP architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PP data-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PP address-unit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PP program flow control (PFC) unit registers . . . . . . . . . . . 40
PP cache architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PP parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PP-interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
PP data-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PP multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PP program-flow-control unit architecture . . . . . . . . . . . . . . 46
PP address-unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . 48
PP instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PP opcode formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
EALU operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
TC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
local memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
external memory timing examples . . . . . . . . . . . . . . . . . . . . 73
host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
absolute maximum ratings over specified temperature
ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
recommended operating conditions . . . . . . . . . . . . . . . . . . 129
electrical characteristics over recommended range of
supply voltage and specified temperature . . . . . . . . 129
signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
timing parameter symbology . . . . . . . . . . . . . . . . . . . . . . . . 131
general notes on timing parameters . . . . . . . . . . . . . . . . . . 132
CLKIN timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . 132
local-bus switching characteristics over full operating
range: CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
device reset timing requirements . . . . . . . . . . . . . . . . . . . . 133
local bus timing requirements: cycle configuration
inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
local bus timing: cycle completion inputs . . . . . . . . . . . . . . 135
general output signal characteristics over operating
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
local bus timing: 2-cycle/column CAS timing . . . . . . . . . . 141
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
XPT input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
host-interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
video interface timing: SCLK timing . . . . . . . . . . . . . . . . . . 145
video interface timing: FCLK input and video outputs . . 146
video interface timing: external sync inputs . . . . . . . . . . . 147
emulator interface connection . . . . . . . . . . . . . . . . . . . . . . . 148
MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
description
The SMJ320C80 is a single-chip, MIMD parallel processor capable of performing over two billion operations
per second. It consists of a 32-bit RISC master processor with a 100-MFLOPS (million floating-point operations
per second) IEEE floating-point unit, four 32-bit parallel processing digital signal processors (DSPs), a transfer
controller with up to 400-MBps off-chip transfer rate, and a video controller. All the processors are coupled tightly
through an on-chip crossbar that provides shared access to on-chip RAM. This performance and
programmability make the ’C80 ideally suited for video, imaging, and high-speed telecommunications
applications.
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443



Part Number SM320C80
Description Digital Signal Processor
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