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SMJ320C6203 Datasheet Preview

SMJ320C6203 Datasheet

Digital Signal Processor

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SMJ320C6203
SGUS033A – FEBRUARY 2002 – REVISED MAY 2016
SMJ320C6203 Fixed-Point Digital Signal Processor
1 Features
1 High-Performance Fixed-Point Digital Signal
Processor (DSP) SMJ320C62x™
– 5-ns Instruction Cycle Time
– 200-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 1600 Million Instructions per Second (MIPS)
• 429-Pin Ball Grid Array (BGA) Package (GLP
Suffix)
• VelociTI™ Advanced Very-Long-Instruction-Word
(VLIW) C62x™ DSP Core
– Eight Highly-Independent Functional Units:
– Six Arithmetic Logic Units (ALUs) (32-/40-
Bit)
– Two 16-Bit Multipliers (32-Bit Result)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
• Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
• 7Mb On-Chip SRAM
– 3Mb Internal Program/Cache (96K 32-Bit
Instructions)
– 4Mb Dual-Access Internal Data (512KB)
– Organized as Two 256KB Blocks for Improved
Concurrency
• Flexible Phase-Locked-Loop (PLL) Clock
Generator
• 32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous Memories:
SDRAM or SBSRAM
– Glueless Interface to Asynchronous Memories:
SRAM and EPROM
– 52MB Addressable External Memory Space
• Four-Channel Bootloading Direct-Memory-Access
(DMA) Controller With an Auxiliary Channel
• 32-Bit Expansion Bus Glueless/Low-Glue
Interface to Popular PCI Bridge Chips
– Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous Microprocessor
Buses
– Master/Slave Functionality
– Glueless Interface to Synchronous FIFOs and
Asynchronous Peripherals
• Three Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral Interface (SPI) Compatible
(Motorola®)
• Two 32-Bit General-Purpose Timers
• IEEE-1149.1 (JTAG(2)) Boundary-Scan-
Compatible
• 0.15-μm/5-Level Metal Process
– CMOS Technology
• 3.3-V I/Os, 1.5-V Internal
2 Description
The SMJ320C6203 device is part of the SMJ320C62x
fixed-point DSP generation in the SMJ320C6000
DSP platform. The C62x DSP devices are based on
the high-performance, advanced VelociTI VLIW
architecture developed by TI, making these DSPs an
excellent choice for multichannel and multifunction
applications.
The SMJ320C62x DSP offers cost-effective solutions
to high-performance DSP-programming challenges.
The SMJ320C6203 has a performance capability of
up to 1600 MIPS at a clock rate of 200 MHz. The
C6203 DSP possesses the operational flexibility of
high-speed controllers and the numerical capability of
array processors. This processor has 32 general-
purpose registers of 32-bit word length and eight
highly-independent functional units.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SMJ320C6203
CFCBGA (429)
27.00 mm × 27.00 mm
× 2.26 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and
Boundary Scan Architecture.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.




etcTI

SMJ320C6203 Datasheet Preview

SMJ320C6203 Datasheet

Digital Signal Processor

No Preview Available !

SMJ320C6203
SGUS033A – FEBRUARY 2002 – REVISED MAY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Description ............................................................. 1
3 Revision History..................................................... 3
4 Description (continued)......................................... 4
5 Characteristics of the C6203 DSP ........................ 4
6 Pin Configuration and Functions ......................... 5
7 Specifications....................................................... 12
7.1 Absolute Maximum Ratings .................................... 12
7.2 Recommended Operating Conditions..................... 12
7.3 Thermal Information ................................................ 12
7.4 Electrical Characteristics......................................... 13
7.5 Timing Requirements for CLKIN (PLL Used).......... 13
7.6 Timing Requirements for CLKIN [PLL Bypassed
(x1)] .......................................................................... 13
7.7 Timing Requirements for XCLKIN........................... 13
7.8 Timing Requirements for Asynchronous Memory
Cycles ...................................................................... 14
7.9 Timing Requirements for Synchronous-Burst SRAM
Cycles ...................................................................... 14
7.10 Timing Requirements for Synchronous DRAM
Cycles ...................................................................... 14
7.11 Timing Requirements for the HOLD/HOLDA
Cycles ...................................................................... 14
7.12 Timing Requirements for Reset ............................ 15
7.13 Timing Requirements for Interrupt Response
Cycles ...................................................................... 15
7.14 Timing Requirements for Synchronous FIFO
Interface ................................................................... 15
7.15 Timing Requirements for Asynchronous Peripheral
Cycles ...................................................................... 15
7.16 Timing Requirements With External Device as Bus
Master ...................................................................... 16
7.17 Timing Requirements With C62x as Bus Master .. 16
7.18 Timing Requirements With External Device as
Asynchronous Bus Master ....................................... 16
7.19 Timing Requirements for Expansion Bus Arbitration
(Internal Arbiter Enabled)......................................... 17
7.20 Timing Requirements for McBSP.......................... 17
7.21 Timing Requirements for FSR when GSYNC = 1. 17
7.22 Timing Requirements for McBSP as SPI Master or
Slave: CLKSTP = 10b, CLKXP = 0.......................... 18
7.23 Timing Requirements for McBSP as SPI Master or
Slave: CLKSTP = 11b, CLKXP = 0.......................... 18
7.24 Timing Requirements for McBSP as SPI Master or
Slave: CLKSTP = 10b, CLKXP = 1.......................... 18
7.25 Timing Requirements for McBSP as SPI Master or
Slave: CLKSTP = 11b, CLKXP = 1.......................... 18
7.26 Timing Requirements for Timer Inputs.................. 18
7.27 Timing Requirements for JTAG Test Port............. 19
7.28 Switching Characteristics for CLKOUT2 ............... 20
7.29 Switching Characteristics for XFCLK .................... 20
7.30 Asynchronous Memory Timing Switching
Characteristics ......................................................... 20
7.31 Switching Characteristics for Synchronous-Burst
SRAM Cycles........................................................... 21
7.32 Switching Characteristics for Synchronous DRAM
Cycles ..................................................................... 21
7.33 Switching Characteristics for the HOLD/HOLDA
Cycles ...................................................................... 22
7.34 Switching Characteristics for Reset ...................... 22
7.35 Switching Characteristics for Interrupt Response
Cycles ...................................................................... 22
7.36 Switching Characteristics for Synchronous FIFO
Interface ................................................................... 23
7.37 Switching Characteristics for Asynchronous
Peripheral Cycles ..................................................... 23
7.38 Switching Characteristics With External Device as
Bus Master ............................................................... 23
7.39 Switching Characteristics With C62x as Bus
Master ...................................................................... 24
7.40 Switching Characteristics With External Device as
Asynchronous Bus Master ....................................... 24
7.41 Switching Characteristics for Expansion Bus
Arbitration (Internal Arbiter Enabled) ....................... 24
7.42 Switching Characteristics for Expansion Bus
Arbitration (Internal Arbiter Disabled)....................... 24
7.43 Switching Characteristics for McBSP.................... 25
7.44 Switching Characteristics for McBSP as SPI Master
or Slave .................................................................... 26
7.45 Switching Characteristics for McBSP as SPI Master
or Slave: CLKSTP = 11b, CLKXP = 0 ..................... 26
7.46 Switching Characteristics for McBSP as SPI Master
or Slave: CLKSTP = 10b, CLKXP = 1 ..................... 27
7.47 Switching Characteristics for McBSP as SPI Master
or Slave: CLKSTP = 11b, CLKXP = 1 ..................... 27
7.48 Switching Characteristics for DMAC Outputs ....... 28
7.49 Switching Characteristics for Timer Outputs......... 28
7.50 Switching Characteristics for Power-Down
Outputs..................................................................... 28
7.51 Switching Characteristics for JTAG Test Port....... 28
8 Parameter Measurement Information ................ 29
8.1 Signal Transition Levels .......................................... 29
8.2 Timing Parameters and Board Routing Analysis .... 30
9 Detailed Description ............................................ 51
9.1 Functional Block Diagram ....................................... 51
9.2 Feature Description................................................. 52
9.3 Register Maps ......................................................... 59
10 Application and Implementation........................ 65
10.1 Typical Application ............................................... 65
11 Power Supply Recommendations ..................... 66
11.1 Power-Supply Sequencing.................................... 66
11.2 System-Level Design Considerations ................... 66
11.3 Power-Supply Design Considerations .................. 66
12 Device and Documentation Support ................. 67
12.1 Device Support...................................................... 67
12.2 Documentation Support ........................................ 68
12.3 Community Resources.......................................... 69
12.4 Trademarks ........................................................... 69
12.5 Electrostatic Discharge Caution ............................ 69
12.6 Glossary ................................................................ 69
13 Mechanical, Packaging, and Orderable
Information ........................................................... 69
2
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Part Number SMJ320C6203
Description Digital Signal Processor
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