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SMJ320F240 Datasheet Preview

SMJ320F240 Datasheet

DSP CONTROLLER

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D Processed to MIL-PRF-38535 (QML)
D High-Performance Static CMOS Technology
D Includes the T320C2xLP Core CPU
-- Object Compatible With the TMS320C2xx
Family
-- Source Code Compatible With
SMJ320C25
-- Upwardly Compatible With SMJ320C50
-- 50-ns Instruction Cycle Time
D Memory
-- 544 Words × 16 Bits of On-Chip
Data/Program Dual-Access RAM
-- 16K Words × 16 Bits of On-Chip Program
Flash EEPROM
-- 224K Words × 16 Bits of Total Memory
Address Reach (64K Data, 64K Program
and 64K I/O, and 32K Global Memory
Space)
D Event-Manager Module
-- 12 Compare/Pulse-Width Modulation
(PWM) Channels
-- Three 16-Bit General-Purpose Timers
With Six Modes, Including Continuous
Upand Up/Down Counting
-- Three 16-Bit Full-Compare Units With
Deadband
-- Three 16-Bit Simple-Compare Units
-- Four Capture Units (Two With
Quadrature Encoder-Pulse Interface
Capability)
SMJ320F240
DSP CONTROLLER
SGUS029C -- APRIL 1999 -- REVISED SEPTEMBER 2004
D Dual 10-Bit Analog-to-Digital Conversion
Module
D 28 Individually Programmable, Multiplexed
I/O Pins
D Phase-Locked-Loop (PLL)-Based Clock
Module
D Watchdog Timer Module (With Real-Time
Interrupt)
D Serial Communications Interface (SCI)
Module
D Serial Peripheral Interface (SPI) Module
D Six External Interrupts (Power Drive
Protect, Reset, NMI, and Three Maskable
Interrupts)
D Four Power-Down Modes for Low-Power
Operation
D Scan-Based Emulation
D Development Tools Available:
-- Texas Instruments (TI) ANSI
C Compiler, Assembler/Linker, and
C-Source Debugger
-- Scan-Based Self-Emulation (XDS510)
-- Third-Party Digital Motor Control and
Fuzzy-Logic Development Support
D --55°C to 125°C Operating Temperature
Range, QML Processing
D 132-Pin Ceramic Quad Flat Package
(HFP Suffix)
description
The SMJ320F240 is a member of a family of digital signal processor (DSP) controllers based on the
TMS320C2xx generation of 16-bit fixed-point DSPs. This family is optimized for digital motor/motion control
applications and contains 16K words of flash memory on chip. The DSP controller combines the enhanced
TMS320 architectural design of the C2xLP core CPU for low-cost, high-performance processing capabilities
and several advanced peripherals optimized for motor/motion control applications. These peripherals include
the event manager module, which provides general-purpose timers and compare registers to generate up to
12 PWM outputs, and a dual 10-bit analog-to-digital converter (ADC), which can perform two simultaneous
conversions within 6.1 μs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI and XDS510 are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
1




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SMJ320F240 Datasheet Preview

SMJ320F240 Datasheet

DSP CONTROLLER

No Preview Available !

SMJ320F240
DSP CONTROLLER
SGUS029C -- APRIL 1999 -- REVISED SEPTEMBER 2004
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Terminal Functions Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Reset and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Functional Block Diagram of the CPU . . . . . . . . . . . . . . . . . . . . 30
DSP Core CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Scan-based Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SMJ320F240 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . 59
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Memory and Peripheral Interface Timing . . . . . . . . . . . . . . . . . . 68
I/O Timing Variation: SPICE Simulation Results . . . . . . . . . . . . 72
READY Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
RS and PORESET Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
XF, BIO, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Timing Event Manager Interface . . . . . . . . . . . . . . . . . . . . . . . . . 77
PWM/CMP Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Capture and QEP Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
General-Purpose Input/Output Timings . . . . . . . . . . . . . . . . . . . 79
Serial Communications Interface (SCI) I/O Timings . . . . . . . . 80
Timing Characteristics for SCI . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SPI Master Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . 81
SPI Slave Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . 85
10-Bit Dual Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . 89
ADC Input Pin Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ADC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Programming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Flash-write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Register File Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
description (continued)
Table 1. Characteristics of the F240 DSP Controller
DEVICE
SMJ320F240
ON-CHIP MEMORY (WORDS)
RAM
FLASH
EEPROM
DATA
DATA/PROG
PROG
288
256
16K
POWER
SUPPLY
(V)
5
CYCLE
TIME
(ns)
50
PACKAGE
TYPE
PIN COUNT
HFP 132--P
The functional block diagram provides a high-level description of each component in the F240 DSP controller.
The SMJ320F240 device is composed of three main functional units: a C2xx DSP core, internal memory, and
peripherals. In addition to these three functional units, there are several system-level features of the F240 that
are distributed. These system features include the memory map, device reset, interrupts, digital input/output
(I/O), clock generation, and low-power operation.
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443



Part Number SMJ320F240
Description DSP CONTROLLER
Maker etcTI
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