SMJ320F240 Datasheet | Texas Instruments

D Processed to MIL-PRF-38535 (QML) D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU -- Object patible With the TMS320C2xx Family -- Source Code patible With SMJ320C25 -- Upwardly patible With SMJ320C50 -- 50-ns Instruction Cycle Time D Memory -- 544 Words × 16 Bits of On-Chip Data/Program Dual-Access RAM -- 16K Words × 16 Bits of On-Chip Program Flash EEPROM -- 224K Words × 16 Bits of Total Memory Address Reach (64K Data, 64K Program and 64K I/O, and 32K Global Memory Space) D Event-Manager Module -- 12 pare/Pulse-Width Modulation (PWM) Channels -- Three 16-Bit General-Purpose Timers With Six Modes, Including Continuous Upand Up/Down Counting -- Three...