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SMOMAPL138B-HIREL Datasheet Preview

SMOMAPL138B-HIREL Datasheet

Low-Power Applications Processor

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SMOMAPL138B-HiRel
www.ti.com
SLVSAQ9B – JANUARY 2011 – REVISED JULY 2013
SMOMAPL138B Low-Power Applications Processor
Check for Samples: SMOMAPL138B-HiRel
1 SMOMAPL138B Low-Power Applications Processor
1.1 Features
123
• Highlights
– Compact 16-Bit Instructions
– Dual Core SoC
• C674x Two Level Cache Memory Architecture
• 375-MHz ARM926EJ-S™ RISC MPU
– 32K-Byte L1P Program RAM/Cache
• 375-MHz C674x Fixed/Floating-Point VLIW
– 32K-Byte L1D Data RAM/Cache
DSP
– 256K-Byte L2 Unified Mapped RAM/Cache
– Enhanced Direct-Memory-Access Controller
– Flexible RAM/Cache Partition (L1 and L2)
(EDMA3)
• Enhanced Direct-Memory-Access Controller 3
– Serial ATA (SATA) Controller
(EDMA3):
– DDR2/Mobile DDR Memory Controller
– 2 Channel Controllers
– Two Multimedia Card (MMC)/Secure Digital
– 3 Transfer Controllers
(SD) Card Interface
– 64 Independent DMA Channels
– LCD Controller
– 16 Quick DMA Channels
– Video Port Interface (VPIF)
– Programmable Transfer Burst Size
– 10/100 Mb/s Ethernet MAC (EMAC):
• TMS320C674x Floating-Point VLIW DSP Core
– Programmable Real-Time Unit Subsystem
– Load-Store Architecture With Non-Aligned
– Three Configurable UART Modules
Support
– USB 1.1 OHCI (Host) With Integrated PHY
– 64 General-Purpose Registers (32 Bit)
– USB 2.0 OTG Port With Integrated PHY
– Six ALU (32-/40-Bit) Functional Units
– One Multichannel Audio Serial Port
• Supports 32-Bit Integer, SP (IEEE Single
– Two Multichannel Buffered Serial Ports
• Dual Core SoC
– 375-MHz ARM926EJ-S™ RISC MPU
– 375-MHz C674x VLIW DSP
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
Approximation (RSQRxP) Operations Per
Cycle
– ARM® Jazelle® Technology
– Two Multiply Functional Units
– EmbeddedICE-RT™ for Real-Time Debug
• Mixed-Precision IEEE Floating Point
• ARM9 Memory Architecture
Multiply Supported up to:
– 16K-Byte Instruction Cache
– 2 SP x SP -> SP Per Clock
– 16K-Byte Data Cache
– 2 SP x SP -> DP Every Two Clocks
– 8K-Byte RAM (Vector Table)
– 2 SP x DP -> DP Every Three Clocks
– 64K-Byte ROM
– 2 DP x DP -> DP Every Four Clocks
• C674x Instruction Set Features
• Fixed Point Multiply Supports Two 32 x
– Superset of the C67x+™ and C64x+™ ISAs
– Up to C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C6000, C6000 are trademarks of Texas Instruments.
2
ARM926EJ-S is a trademark of ARM Limited.
3
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated




etcTI

SMOMAPL138B-HIREL Datasheet Preview

SMOMAPL138B-HIREL Datasheet

Low-Power Applications Processor

No Preview Available !

SMOMAPL138B-HiRel
SLVSAQ9B – JANUARY 2011 – REVISED JULY 2013
www.ti.com
– Protected Mode Operation
– Exceptions Support for Error Detection and
Program Redirection
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• 128K-Byte RAM Shared Memory
• 1.8V or 3.3V LVCMOS IOs (except for USB and
DDR2 interfaces)
• Two External Memory Interfaces:
– EMIFA
• NOR (8-/16-Bit-Wide Data)
• NAND (8-/16-Bit-Wide Data)
• 16-Bit SDRAM With 128 MB Address
Space
– DDR2/Mobile DDR Memory Controller
• 16-Bit DDR2 SDRAM With 512 MB
Address Space or
• 16-Bit mDDR SDRAM With 256 MB
Address Space
• Three Configurable 16550 type UART Modules:
– With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
• LCD Controller
• Two Serial Peripheral Interfaces (SPI) Each
With Multiple Chip-Selects
• Two Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
Interfaces
• Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• One Host-Port Interface (HPI) With 16-Bit-Wide
Muxed Address/Data Bus For High Bandwidth
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime
Unit (PRU) Cores
• 32-Bit Load/Store RISC architecture
• 4K Byte instruction RAM per core
• 512 Bytes data RAM per core
• PRU Subsystem (PRUSS) can be disabled
via software to save power
• Register 30 of each PRU is exported from
the subsystem in addition to the normal
R31 output of the PRU cores.
– Standard power management mechanism
• Clock gating
• Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
• USB 1.1 OHCI (Host) With Integrated PHY
(USB1)
• USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
ISOC) Rx and Tx
• One Multichannel Audio Serial Port:
– Two Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable
– FIFO buffers for Transmit and Receive
• Two Multichannel Buffered Serial Ports:
– Supports TDM, I2S, and Similar Formats
– AC97 Audio Codec Interface
– Telecom Interfaces (ST-Bus, H100)
– 128-channel TDM
– FIFO buffers for Transmit and Receive
• 10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant
– MII Media Independent Interface
– RMII Reduced Media Independent Interface
– Management Data I/O (MDIO) Module
• Video Port Interface (VPIF):
– Two 8-bit SD (BT.656), Single 16-bit or Single
Raw (8-/10-/12-bit) Video Capture Channels
– Two 8-bit SD (BT.656), Single 16-bit Video
Display Channels
• Universal Parallel Port (uPP):
– High-Speed Parallel Interface to FPGAs and
Data Converters
– Data Width on Each of Two Channels is 8- to
16-bit Inclusive
– Single Data Rate or Dual Data Rate Transfers
– Supports Multiple Interfaces with START,
ENABLE and WAIT Controls
• Serial ATA (SATA) Controller:
– Supports SATA I (1.5 Gbps) and SATA II (3.0
Gbps)
– Supports all SATA Power Management
Features
– Hardware-Assisted Native Command
Queueing (NCQ) for up to 32 Entries
– Supports Port Multiplier and Command-
Based Switching
• Real-Time Clock With 32 KHz Oscillator and
Separate Power Rail
• Three 64-Bit General-Purpose Timers (Each
configurable as Two 32-Bit Timers)
• One 64-bit General-Purpose/Watchdog Timer
(Configurable as Two 32-bit General-Purpose
Timers)
• Two Enhanced Pulse Width Modulators
(eHRPWM):
2
SMOMAPL138B Low-Power Applications Processor
Copyright © 2011–2013, Texas Instruments Incorporated
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Product Folder Links: SMOMAPL138B-HiRel



Part Number SMOMAPL138B-HIREL
Description Low-Power Applications Processor
Maker etcTI
Total Page 3 Pages
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