SN10KHT5541 Datasheet | Texas Instruments

- 10KH patible - ECL and TTL Control Inputs - Noninverting Outputs - Flow-Through Architecture Optimizes PCB Layout - Center Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching Noise - Package Options Include “Small Outline” Packages and Standard Plastic 300-mil DIPs description This octal ECL-to-TTL translator is designed to provide a efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. Two output-enable pins, OE1 and OE2, are provided. These control inputs are ANDed together with OE1 being ECL patible and OE2 being TTL patible. This offers the choice of controlling the outputs of the device from either a TTL or ECL signal environment. The SN10KHT5541 is characterized for operation from 0°C to 75°C. FUNCTION TABLE OUTPUT ENABLE OE1 OE2 XH HX LL LL DATA INPUT A X X L H OUTPUT (TTL) Y Z Z L H SN10KHT5541 OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS SDZS003A - OCTOBER 1989 - REVISED OCTOBER 1990 DW OR NT PACKAGE (T0P VIEW) Y1 Y2 Y3 Y4 VCC GND GND GND Y5 Y6 Y7 Y8 1 2 3 4 5 6 7 8 9 10 11 12 24 A1 23 A2 22 A3 21 A4 20 OE2 (TTL) 19 VEE 18 GND 17 OE1 (ECL) 16 A5 15 A6 14 A7 13 A8 logic symbol† OE1 17 OE2 20 ECL/TTL & EN A1...