SN54165 Overview
Key Specifications
Description
The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input.
Key Features
- gated clock (CLK) inputs and complementary outputs from the eighth bit
- All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design
- Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function
- Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input
- Clock inhibit (CLK INH) should be changed to the high level only while CLK is high
