SN54AHCT138 Datasheet | Texas Instruments

Features - Inputs are TTL-voltage patible - Designed specifically for high-speed memory decoders and data-transmission systems - Incorporate three enable inputs to simplify cascading and/or data reception - Latch-up performance exceeds 250m A per JESD - ESD protection exceeds JESD 22 - ±2000V human-body model (A114-A) - ±1000V charged-device model (C101) 2 Description The ’AHCT138 3-line to 8-line decoders/ demultiplexers are designed to be used in highperformance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. PART NUMBER SNx4AHCT138 Device Information PACKAGE (1) PACKAGE SIZE (2) BODY SIZE (3) RGY (VQFN, 16) 4mm x 3.5mm 4mm x 3.5mm N (PDIP, 16) 19.3 mm × 9.4 mm 19.32 mm x 6.35 mm D (SOIC, 16) 9.9 mm × 6 mm 9.90 mm x 3.90 mm NS (SOP, 16) 10.2mm x 7.8mm 10.20 mm x 5.30 mm DB (SSOP, 16) 6.2 mm × 7.8 mm 6.20 mm x 5.30 mm PW (TSSOP , 16) 5 mm × 6.4 mm 5.00 mm x 4.40 mm DGV (TVSOP, 16) 3.6mm x 6.4mm 3.6mm x 4.4mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable (3) The body size (length × width) is a nominal value and does not include pins. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54AHCT138, SN74AHCT138 SCLS266N - DECEMBER 1995 - REVISED APRIL...