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SN54AHCT138 Datasheet Preview

SN54AHCT138 Datasheet

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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SN54AHCT138, SN74AHCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
D Inputs Are TTL-Voltage Compatible
D Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
D Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
SCLS266M − DECEMBER 1995 − REVISED JULY 2003
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54AHCT138 . . . J OR W PACKAGE
SN74AHCT138 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
A1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
GND 8
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
SN74AHCT138 . . . RGY PACKAGE
(TOP VIEW)
1
B2
C3
G2A 4
G2B 5
G1 6
Y7 7
8
16
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9
SN54AHCT138 . . . FK PACKAGE
(TOP VIEW)
C
G2A
NC
G2B
G1
3 2 1 20 19
4
18 Y1
5
17 Y2
6
16 NC
7
15 Y3
8
14 Y4
9 10 11 12 13
NC − No internal connection
description/ordering information
The ’AHCT138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance
memory-decoding and data-routing applications that require very short propagation-delay times. In
high-performance memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and
the enable time of the memory usually are less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Tape and reel SN74AHCT138RGYR HB138
PDIP − N
Tube
SN74AHCT138N
SN74AHCT138N
SOIC − D
Tube
Tape and reel
SN74AHCT138D
SN74AHCT138DR
AHCT138
−40°C to 85°C
SOP − NS
Tape and reel SN74AHCT138NSR
AHCT138
SSOP − DB
Tape and reel SN74AHCT138DBR
HB138
TSSOP − PW
Tube
Tape and reel
SN74AHCT138PW
SN74AHCT138PWR
HB138
TVSOP − DGV
Tape and reel SN74AHCT138DGVR HB138
CDIP − J
Tube
SNJ54AHCT138J
SNJ54AHCT138J
−55°C to 125°C CFP − W
Tube
SNJ54AHCT138W
SNJ54AHCT138W
LCCC − FK
Tube
SNJ54AHCT138FK
SNJ54AHCT138FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1




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SN54AHCT138 Datasheet Preview

SN54AHCT138 Datasheet

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

No Preview Available !

SN54AHCT138, SN74AHCT138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS266M − DECEMBER 1995 − REVISED JULY 2003
description/ordering information (continued)
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1 G2A G2B C
B
A
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
logic diagram (positive logic)
1
A
Select
Inputs
2
B
3
C
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
Data
Outputs
10
Y5
Enable
Inputs
4
G2A
5
G2B
6
G1
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
9
Y6
7
Y7
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Part Number SN54AHCT138
Description 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
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