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SN54AHCT174 - HEX D-TYPE FLIP-FLOPS

Description

These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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D Inputs Are TTL-Voltage Compatible D Contain Six Flip-Flops With Single-Rail Outputs D Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK.
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